From dcc24c3645b3878bf3454345dbcfdf7ef1a0ba10 Mon Sep 17 00:00:00 2001 From: biouman <> Date: Sun, 15 Apr 2001 11:20:38 +0000 Subject: *** empty log message *** --- include/Makefile.am | 2 +- include/alu.h | 2 +- include/archi.h | 21 ---- include/fpu.h | 2 +- include/interne.h | 2 +- include/memoire.h | 2 +- include/registre.h | 2 +- include/simulator.h | 21 ++++ lib/Makefile.am | 2 +- lib/archi.c | 349 --------------------------------------------------- lib/fpu.c | 2 +- lib/interne.c | 2 +- lib/memoire.c | 2 +- lib/registre.c | 2 +- lib/simulator.c | 351 ++++++++++++++++++++++++++++++++++++++++++++++++++++ po/POTFILES.in | 2 +- po/ProjetArchi.pot | 2 +- 17 files changed, 385 insertions(+), 383 deletions(-) delete mode 100644 include/archi.h create mode 100644 include/simulator.h delete mode 100644 lib/archi.c create mode 100644 lib/simulator.c diff --git a/include/Makefile.am b/include/Makefile.am index c0bc500..9bfd99d 100644 --- a/include/Makefile.am +++ b/include/Makefile.am @@ -1 +1 @@ -include_HEADERS = alu.h archi.h assembler.h exceptions.h fpu.h hash.h interne.h memoire.h meta.h numbers.h parser.h registre.h types.h +include_HEADERS = alu.h simulator.h assembler.h exceptions.h fpu.h hash.h interne.h memoire.h meta.h numbers.h parser.h registre.h types.h diff --git a/include/alu.h b/include/alu.h index 916a626..80a5d73 100644 --- a/include/alu.h +++ b/include/alu.h @@ -1,6 +1,6 @@ #ifndef __ALU_H__ #define __ALU_H__ -#include "archi.h" +#include "types.h" Uint32 AdditionNonSigne(Uint32 a, Uint32 b); Uint32 AdditionSigne(Uint32 a, Uint32 b); diff --git a/include/archi.h b/include/archi.h deleted file mode 100644 index 2520343..0000000 --- a/include/archi.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __ARCHI_H__ -#define __ARCHI_H__ - -#define TAILLE_MEMOIRE 1024 /* Nombre maximum de mots que peut contenir la mémoire principale */ -#define NB_REGISTRES_PHYSIQUES 64 /* Nombre réel de registres */ -#define NB_REGISTRES_UTILISABLES 32 /* Nombre de registres que le processeur a à sa disposition */ -#define REG_RG 32 /* Numero du registre Rg */ -#define REG_RD 33 /* Numero du registre Rd */ -#define REG_PC 34 /* Numero du registre PC */ -#define REG_FLAG 35 /* Numero du registre de flags */ -#define REG_PUSHPOP 36 /* Numero du registre de Push-Pop */ -#define ADD_PP (TAILLE_MEMOIRE-1) /* Emplacement de la pile */ - -typedef unsigned long int Uint32; /* type d'un mot mémoire (32 bits) */ - -Uint32 memoire_principale[TAILLE_MEMOIRE]; -Uint32 registre[NB_REGISTRES_PHYSIQUES]; /* Registres classiques */ -Uint32 Err_Mem; /* en cas d'erreur l/e en mémoire principale */ -Uint32 Err_Reg; /* en cas d'erreur l/e dans un registre */ - -#endif diff --git a/include/fpu.h b/include/fpu.h index b10edfd..ea98e74 100644 --- a/include/fpu.h +++ b/include/fpu.h @@ -1,6 +1,6 @@ #ifndef __FPU_H__ #define __FPU_H__ -#include "archi.h" +#include "types.h" void fpu(Uint32 opcode); #endif \ No newline at end of file diff --git a/include/interne.h b/include/interne.h index 2dac208..2f91050 100644 --- a/include/interne.h +++ b/include/interne.h @@ -1,6 +1,6 @@ #ifndef __INTERNE_H__ #define __INTERNE_H__ -#include "archi.h" +#include "types.h" #define VAL_MAX 4294967295 void Reset(Uint32 * i); void Set(Uint32 * i); diff --git a/include/memoire.h b/include/memoire.h index 2fd8b8b..0598039 100644 --- a/include/memoire.h +++ b/include/memoire.h @@ -1,6 +1,6 @@ #ifndef __MEMOIRE_H__ #define __MEMOIRE_H__ -#include "archi.h" +#include "types.h" Uint32 LD(Uint32 offset); void ST(Uint32 offset, Uint32 valeur); #endif \ No newline at end of file diff --git a/include/registre.h b/include/registre.h index e7b9ff6..f5d8b5b 100644 --- a/include/registre.h +++ b/include/registre.h @@ -1,7 +1,7 @@ #ifndef __REGISTRE_H__ #define __REGISTRE_H__ -#include "archi.h" +#include "types.h" Uint32 LireRegistreRG(void); Uint32 LireRegistreRD(void); diff --git a/include/simulator.h b/include/simulator.h new file mode 100644 index 0000000..e2df994 --- /dev/null +++ b/include/simulator.h @@ -0,0 +1,21 @@ +#ifndef __SIMULATOR_H__ +#define __SIMULATOR_H__ + +#define TAILLE_MEMOIRE 1024 /* Nombre maximum de mots que peut contenir la mémoire principale */ +#define NB_REGISTRES_PHYSIQUES 64 /* Nombre réel de registres */ +#define NB_REGISTRES_UTILISABLES 32 /* Nombre de registres que le processeur a à sa disposition */ +#define REG_RG 32 /* Numero du registre Rg */ +#define REG_RD 33 /* Numero du registre Rd */ +#define REG_PC 34 /* Numero du registre PC */ +#define REG_FLAG 35 /* Numero du registre de flags */ +#define REG_PUSHPOP 36 /* Numero du registre de Push-Pop */ +#define ADD_PP (TAILLE_MEMOIRE-1) /* Emplacement de la pile */ + +#include "types.h" + +Uint32 memoire_principale[TAILLE_MEMOIRE]; +Uint32 registre[NB_REGISTRES_PHYSIQUES]; /* Registres classiques */ +Uint32 Err_Mem; /* en cas d'erreur l/e en mémoire principale */ +Uint32 Err_Reg; /* en cas d'erreur l/e dans un registre */ + +#endif diff --git a/lib/Makefile.am b/lib/Makefile.am index f6172b3..b760f64 100644 --- a/lib/Makefile.am +++ b/lib/Makefile.am @@ -5,7 +5,7 @@ INCLUDES = -I. -I.. -I$(includedir) -I../include lib_LTLIBRARIES = libCompilo.la libSimul.la libCompilo_la_SOURCES = assembler.c parser.c meta.c numbers.c hash.c exceptions.c -libSimul_la_SOURCES = alu.c archi.c exceptions.c fpu.c interne.c memoire.c registre.c +libSimul_la_SOURCES = alu.c simulator.c exceptions.c fpu.c interne.c memoire.c registre.c libCompilo_la_LDFLAGS = -version-info $(ProjetArchi_VERSION_INFO) libSimul_la_LFDLAGS = -version-info $(ProjetArchi_VERSION_INFO) diff --git a/lib/archi.c b/lib/archi.c deleted file mode 100644 index cb8bb4a..0000000 --- a/lib/archi.c +++ /dev/null @@ -1,349 +0,0 @@ -#include - -#ifdef HAVE_CONFIG_H -#include "config.h" -#else -#define _(x) x -#endif - -#include "alu.h" -#include "registre.h" -#include "memoire.h" -#include "fpu.h" - - - - -// a modifier : Adresse switch 0 c faux -// CALL RET ??? -// verifier le reste - -// initialisation de la MP avec un malloc -// fermeture du prog et free -// catch du ctrl-c - -Uint32 LireInstruction(void) -{ - return (LD(LireRegistrePC())); -} - -void IncrementeCompteurOrdinal(void) -{ - EcrireRegistrePC(AdditionNonSigne(LireRegistrePC(), 1)); -} - -Uint32 Adresse(Uint32 u, Uint32 instruction) -{ - switch (champ(u, 2)) { - case 0: - return (LireRegistre(Champ3(instruction))); /* directement registre A CORRIGER */ - case 1: - IncrementeCompteurOrdinal(); - return (LireInstruction()); - case 2: - return (LireRegistre(Champ3(instruction))); /* Adresse dans registre */ - case 3: - IncrementeCompteurOrdinal(); - return (LireRegistre(Champ3(instruction)) + LireInstruction()); /* Adresse dans registre + decalage de nouvelle instruction */ - default: /* Il exige une loge... */ - return (0); - } -} - -void Initialisation(void) -{ - int i; - - Reset(&Err_Mem); - Reset(&Err_Reg); - for (i = 0; i < TAILLE_MEMOIRE; i++) - Reset(&memoire_principale[i]); - EcrireRegistrePP(ADD_PP); -} - -void Decode(Uint32 instruction) -{ - Uint32 champ_registre_resultat, val1, val2, resultat; - - if (Opcode(instruction) & 0x80) { - fpu(Opcode(instruction)); - } else { - switch (Opcode(instruction)) { - case (0 || 1 || 2 || 3 || 4 || 5):{ - /* ALU */ - champ_registre_resultat = Champ1(instruction); /* Champ du registre dans lequel va etre stocké le résultat */ - val1 = LireRegistre(Champ2(instruction)); /* Premier entier qui va etre utilisé dans l'opération */ - if (ValeurBit(Extension(instruction), 0) == 0) - val2 = LireRegistre(Champ3(instruction)); /* Deuxième entier, stocké dans un registre, qui va etre utilisé dans l'opération */ - else { - IncrementeCompteurOrdinal(); - val2 = LireInstruction(); /* Deuxième entier, stocké après l'instruction, qui va etre utilisé dans l'opération */ - } - if (ValeurBit(Extension(instruction), 1) == 0) /* Teste si l'opération est signée ou pas */ - switch (Opcode(instruction)) { - case 0: - resultat = AdditionNonSigne(val1, val2); - break; - case 1: - resultat = SoustractionNonSigne(val1, val2); - break; - case 2: - resultat = MultiplicationNonSigne(val1, val2); - break; - case 3: - resultat = DivisionNonSigne(val1, val2); - break; - case 4: - resultat = AND(val1, val2); - break; - case 5: - resultat = OR(val1, val2); - break; - case 6: - resultat = SHL(val1); - break; - case 7: - resultat = SHR(val1); - break; - } else - switch (Opcode(instruction)) { - case 0: - resultat = AdditionSigne(val1, val2); - break; - case 1: - resultat = SoustractionSigne(val1, val2); - break; - case 2: - resultat = MultiplicationSigne(val1, val2); - break; - case 3: - resultat = DivisionSigne(val1, val2); - break; - case 4: - resultat = AND(val1, val2); - break; - case 5: - resultat = OR(val1, val2); - break; - case 6: - resultat = SHL(val1); - break; - case 7: - resultat = SHR(val1); - break; - } - EcrireRegistre(champ_registre_resultat, resultat); /* On écrit le résultat dans le registre de sortie */ - break; - } - case 8:{ /* MOV <=> il exige une loge en losange ou la sauje jonche les sieges */ - if (ValeurBit(Extension(instruction), 4) == 1) /* MOV conditionnel */ - if (ValeurBit(Extension(instruction), 5) == 0) /* Test normal */ - switch (champ(Extension(instruction) >> 2, 4)) { /* teste les bits 2 et 3 */ - case 0: - if (Overflow() == 1) - goto fin; - case 1: - if (Zero() == 1) - goto fin; - case 2: - if (Sign() == 1) - goto fin; - case 3: - if (Parity() == 1) - goto fin; - } else /* Negation du test */ - switch (champ(Extension(instruction) >> 2, 4)) { /* teste les bits 2 et 3 */ - case 0: - if (Overflow() == 0) - goto fin; - case 1: - if (Zero() == 0) - goto fin; - case 2: - if (Sign() == 0) - goto fin; - case 3: - if (Parity() == 0) - goto fin; - } - /* Pas de MOV conditionnel */ - if (ValeurBit(Extension(instruction), 1) == 0) /* Mov arg1 arg2 */ - if (ValeurBit(Extension(instruction), 0) == 0) /* arg2 = reg */ - EcrireRegistre(Champ1(instruction), LireRegistre(Champ2(instruction))); - else /* arg2 = imm32 */ if (champ(Champ2(instruction), 4) == 0) - EcrireRegistre(Champ1(instruction), - Adresse(Champ2(instruction), instruction)); - else - EcrireRegistre(Champ1(instruction), - LD(Adresse(Champ2(instruction), instruction))); - else /* Mov arg2 arg1 */ if (ValeurBit(Extension(instruction), 0) == 0) /* arg2 = reg */ - EcrireRegistre(Champ2(instruction), LireRegistre(Champ1(instruction))); - else /* arg1 = imm32 */ if (champ(Champ2(instruction), 4) == 0) - ST(Adresse(Champ2(instruction), instruction), - LireRegistre(Champ1(instruction))); - else - ST(Adresse(Champ2(instruction), instruction), - LireRegistre(Champ1(instruction))); - fin: - break; - } - case 9:{ /* NOP */ - /* Instruction nulle */ - break; - } - case 10: /* J */ - case 11:{ - int test1, test2; - - switch (champ(Extension(instruction), 4)) { - case 0: - test1 = LireRegistre(Champ1(instruction)) == LireRegistre(Champ2(instruction)); - break; - case 1: - test1 = LireRegistre(Champ1(instruction)) != LireRegistre(Champ2(instruction)); - break; - case 2: - test1 = LireRegistre(Champ1(instruction)) < LireRegistre(Champ2(instruction)); - break; - case 3: - test1 = LireRegistre(Champ1(instruction)) <= LireRegistre(Champ2(instruction)); - break; - } - switch (champ(Extension(instruction) >> 2, 4)) { - case 0: - test2 = Overflow(); - break; - case 1: - test2 = Zero(); - break; - case 2: - test2 = Sign(); - break; - case 3: - test2 = Parity(); - break; - } - switch (champ(Extension(instruction) >> 4, 4)) { - case 0: - test1 = test1; - break; - case 1: - test1 = test1 || test2; - break; - case 2: - test1 = test1 && !test2; - break; - case 3: - test1 = test1 || !test2; - break; - } - if (test1) { - IncrementeCompteurOrdinal(); - if (Opcode(instruction) == 10) - EcrireRegistrePC(LireInstruction()); - else - EcrireRegistrePC(AdditionNonSigne(LireRegistrePC(), LireInstruction())); - } - break; - } - case (12): /* JMP *//* Kris Kross */ - case (13): - if (ValeurBit(Extension(instruction), 0) == 0) { - ; /* RET */ - } else if (ValeurBit(Extension(instruction), 1) == 0) ; /* JMP */ - else; /* CALL */ - - break; - case 14:{ /* PUSH */ - Uint32 val; /* valeur qui va etre stockée */ - - EcrireRegistrePP(SoustractionNonSigne(LireRegistrePP(), 1)); /* On pointe sur un emplacement vide */ - if (ValeurBit(Extension(instruction), 0) == 0) - val = LireRegistre(Champ1(instruction)); - else { - IncrementeCompteurOrdinal(); - val = LireInstruction(); - } - ST(LireRegistrePP(), val); - break; - } - case 15:{ /* POP */ - EcrireRegistre(Champ1(instruction), LireRegistrePP()); - EcrireRegistrePP(AdditionNonSigne(LireRegistrePP(), 1)); - break; - } - case 127:{ /* HALT-RESET */ - if (ValeurBit(Extension(instruction), 0)) - getc(stdin); /* Halt */ - else - Initialisation(); /* Reset */ - break; - } - default:{ - printf("soja"); - } - } - } -} -void Traitement(void) -{ - Uint32 instruction; - - while (!0) { - instruction = LireInstruction(); - Decode(instruction); - IncrementeCompteurOrdinal(); - } -} - -void Debogueur(void) // transformer en affiche reg -{ - int i,j; - -/* gotoxy(1, 1); - printf("Etat des registres classiques Etat des registres"); - gotoxy(1, 2); - printf(" speciaux "); - gotoxy(1, 11); - printf(" Instruction a decoder"); - gotoxy(1, 14); - printf(" Prochaine instruction"); - for (i = 1; i <= 16; i++) { - gotoxy(1, i + 2); - printf("r%2d:%9d", i - 1, registre[i - 1]); - } - for (i = 17; i <= 32; i++) { - gotoxy(17, i - 16 + 2); - printf("r%2d:%9d", i - 1, registre[i - 1]); - } - gotoxy(40, 4); - printf("Rg :%9d", LireRegistreRG()); - gotoxy(40, 5); - printf("Rd :%9d", LireRegistreRD()); - gotoxy(40, 6); - printf("PC :%9d", LireRegistrePC()); - gotoxy(40, 7); - printf("Flag :%9d", LireRegistreFLAG()); - gotoxy(40, 12); - printf(" %9d", LireInstruction()); - registre[REG_PC]++; - gotoxy(40, 15); - printf(" %9d", LireInstruction()); - registre[REG_PC]--; - getc(stdin); -*/ - for (i=0; i<=3; i++) { - for (j=1; j<=8;j++) { - printf(" R%02d ", (i*8+j)); - } - printf("\n"); - for (j=1; j<=8;j++) { - printf("%08lX ", (registre[i*8+j-1])); - } - printf("\n"); - - } - printf("Rg: %08lX | Rd: %08lX | Flag: %08lX | PC: %08lX\n", LireRegistreRG(), LireRegistreRD(), LireRegistreFLAG(),registre[REG_PC]); - printf("\n"); -} - diff --git a/lib/fpu.c b/lib/fpu.c index c14c87d..bb59aa3 100644 --- a/lib/fpu.c +++ b/lib/fpu.c @@ -1,5 +1,5 @@ #include "fpu.h" -#include "archi.h" +#include "types.h" #include "exceptions.h" #ifdef HAVE_CONFIG_H diff --git a/lib/interne.c b/lib/interne.c index bdab97e..05c4332 100644 --- a/lib/interne.c +++ b/lib/interne.c @@ -1,6 +1,6 @@ #include #include "interne.h" -#include "archi.h" +#include "simulator.h" // mettre des exceptions dans les fcns ci dessous a la place de GestionErreurs diff --git a/lib/memoire.c b/lib/memoire.c index c8dd6a4..0bbd367 100644 --- a/lib/memoire.c +++ b/lib/memoire.c @@ -1,6 +1,6 @@ #include "memoire.h" #include "interne.h" -#include "archi.h" +#include "simulator.h" /*****************************************/ /** **/ diff --git a/lib/registre.c b/lib/registre.c index f97595d..ccd284c 100644 --- a/lib/registre.c +++ b/lib/registre.c @@ -1,6 +1,6 @@ #include "registre.h" #include "interne.h" -#include "archi.h" +#include "simulator.h" /*****************************************/ /** **/ diff --git a/lib/simulator.c b/lib/simulator.c new file mode 100644 index 0000000..ac1dae4 --- /dev/null +++ b/lib/simulator.c @@ -0,0 +1,351 @@ +#include + +#ifdef HAVE_CONFIG_H +#include "config.h" +#else +#define _(x) x +#endif + +#include "alu.h" +#include "simulator.h" +#include "interne.h" +#include "registre.h" +#include "memoire.h" +#include "fpu.h" + + + + +// a modifier : Adresse switch 0 c faux +// CALL RET ??? +// verifier le reste + +// initialisation de la MP avec un malloc +// fermeture du prog et free +// catch du ctrl-c + +Uint32 LireInstruction(void) +{ + return (LD(LireRegistrePC())); +} + +void IncrementeCompteurOrdinal(void) +{ + EcrireRegistrePC(AdditionNonSigne(LireRegistrePC(), 1)); +} + +Uint32 Adresse(Uint32 u, Uint32 instruction) +{ + switch (champ(u, 2)) { + case 0: + return (LireRegistre(Champ3(instruction))); /* directement registre A CORRIGER */ + case 1: + IncrementeCompteurOrdinal(); + return (LireInstruction()); + case 2: + return (LireRegistre(Champ3(instruction))); /* Adresse dans registre */ + case 3: + IncrementeCompteurOrdinal(); + return (LireRegistre(Champ3(instruction)) + LireInstruction()); /* Adresse dans registre + decalage de nouvelle instruction */ + default: /* Il exige une loge... */ + return (0); + } +} + +void Initialisation(void) +{ + int i; + + Reset(&Err_Mem); + Reset(&Err_Reg); + for (i = 0; i < TAILLE_MEMOIRE; i++) + Reset(&memoire_principale[i]); + EcrireRegistrePP(ADD_PP); +} + +void Decode(Uint32 instruction) +{ + Uint32 champ_registre_resultat, val1, val2, resultat; + + if (Opcode(instruction) & 0x80) { + fpu(Opcode(instruction)); + } else { + switch (Opcode(instruction)) { + case (0 || 1 || 2 || 3 || 4 || 5):{ + /* ALU */ + champ_registre_resultat = Champ1(instruction); /* Champ du registre dans lequel va etre stocké le résultat */ + val1 = LireRegistre(Champ2(instruction)); /* Premier entier qui va etre utilisé dans l'opération */ + if (ValeurBit(Extension(instruction), 0) == 0) + val2 = LireRegistre(Champ3(instruction)); /* Deuxième entier, stocké dans un registre, qui va etre utilisé dans l'opération */ + else { + IncrementeCompteurOrdinal(); + val2 = LireInstruction(); /* Deuxième entier, stocké après l'instruction, qui va etre utilisé dans l'opération */ + } + if (ValeurBit(Extension(instruction), 1) == 0) /* Teste si l'opération est signée ou pas */ + switch (Opcode(instruction)) { + case 0: + resultat = AdditionNonSigne(val1, val2); + break; + case 1: + resultat = SoustractionNonSigne(val1, val2); + break; + case 2: + resultat = MultiplicationNonSigne(val1, val2); + break; + case 3: + resultat = DivisionNonSigne(val1, val2); + break; + case 4: + resultat = AND(val1, val2); + break; + case 5: + resultat = OR(val1, val2); + break; + case 6: + resultat = SHL(val1); + break; + case 7: + resultat = SHR(val1); + break; + } else + switch (Opcode(instruction)) { + case 0: + resultat = AdditionSigne(val1, val2); + break; + case 1: + resultat = SoustractionSigne(val1, val2); + break; + case 2: + resultat = MultiplicationSigne(val1, val2); + break; + case 3: + resultat = DivisionSigne(val1, val2); + break; + case 4: + resultat = AND(val1, val2); + break; + case 5: + resultat = OR(val1, val2); + break; + case 6: + resultat = SHL(val1); + break; + case 7: + resultat = SHR(val1); + break; + } + EcrireRegistre(champ_registre_resultat, resultat); /* On écrit le résultat dans le registre de sortie */ + break; + } + case 8:{ /* MOV <=> il exige une loge en losange ou la sauje jonche les sieges */ + if (ValeurBit(Extension(instruction), 4) == 1) /* MOV conditionnel */ + if (ValeurBit(Extension(instruction), 5) == 0) /* Test normal */ + switch (champ(Extension(instruction) >> 2, 4)) { /* teste les bits 2 et 3 */ + case 0: + if (Overflow() == 1) + goto fin; + case 1: + if (Zero() == 1) + goto fin; + case 2: + if (Sign() == 1) + goto fin; + case 3: + if (Parity() == 1) + goto fin; + } else /* Negation du test */ + switch (champ(Extension(instruction) >> 2, 4)) { /* teste les bits 2 et 3 */ + case 0: + if (Overflow() == 0) + goto fin; + case 1: + if (Zero() == 0) + goto fin; + case 2: + if (Sign() == 0) + goto fin; + case 3: + if (Parity() == 0) + goto fin; + } + /* Pas de MOV conditionnel */ + if (ValeurBit(Extension(instruction), 1) == 0) /* Mov arg1 arg2 */ + if (ValeurBit(Extension(instruction), 0) == 0) /* arg2 = reg */ + EcrireRegistre(Champ1(instruction), LireRegistre(Champ2(instruction))); + else /* arg2 = imm32 */ if (champ(Champ2(instruction), 4) == 0) + EcrireRegistre(Champ1(instruction), + Adresse(Champ2(instruction), instruction)); + else + EcrireRegistre(Champ1(instruction), + LD(Adresse(Champ2(instruction), instruction))); + else /* Mov arg2 arg1 */ if (ValeurBit(Extension(instruction), 0) == 0) /* arg2 = reg */ + EcrireRegistre(Champ2(instruction), LireRegistre(Champ1(instruction))); + else /* arg1 = imm32 */ if (champ(Champ2(instruction), 4) == 0) + ST(Adresse(Champ2(instruction), instruction), + LireRegistre(Champ1(instruction))); + else + ST(Adresse(Champ2(instruction), instruction), + LireRegistre(Champ1(instruction))); + fin: + break; + } + case 9:{ /* NOP */ + /* Instruction nulle */ + break; + } + case 10: /* J */ + case 11:{ + int test1, test2; + + switch (champ(Extension(instruction), 4)) { + case 0: + test1 = LireRegistre(Champ1(instruction)) == LireRegistre(Champ2(instruction)); + break; + case 1: + test1 = LireRegistre(Champ1(instruction)) != LireRegistre(Champ2(instruction)); + break; + case 2: + test1 = LireRegistre(Champ1(instruction)) < LireRegistre(Champ2(instruction)); + break; + case 3: + test1 = LireRegistre(Champ1(instruction)) <= LireRegistre(Champ2(instruction)); + break; + } + switch (champ(Extension(instruction) >> 2, 4)) { + case 0: + test2 = Overflow(); + break; + case 1: + test2 = Zero(); + break; + case 2: + test2 = Sign(); + break; + case 3: + test2 = Parity(); + break; + } + switch (champ(Extension(instruction) >> 4, 4)) { + case 0: + test1 = test1; + break; + case 1: + test1 = test1 || test2; + break; + case 2: + test1 = test1 && !test2; + break; + case 3: + test1 = test1 || !test2; + break; + } + if (test1) { + IncrementeCompteurOrdinal(); + if (Opcode(instruction) == 10) + EcrireRegistrePC(LireInstruction()); + else + EcrireRegistrePC(AdditionNonSigne(LireRegistrePC(), LireInstruction())); + } + break; + } + case (12): /* JMP *//* Kris Kross */ + case (13): + if (ValeurBit(Extension(instruction), 0) == 0) { + ; /* RET */ + } else if (ValeurBit(Extension(instruction), 1) == 0) ; /* JMP */ + else; /* CALL */ + + break; + case 14:{ /* PUSH */ + Uint32 val; /* valeur qui va etre stockée */ + + EcrireRegistrePP(SoustractionNonSigne(LireRegistrePP(), 1)); /* On pointe sur un emplacement vide */ + if (ValeurBit(Extension(instruction), 0) == 0) + val = LireRegistre(Champ1(instruction)); + else { + IncrementeCompteurOrdinal(); + val = LireInstruction(); + } + ST(LireRegistrePP(), val); + break; + } + case 15:{ /* POP */ + EcrireRegistre(Champ1(instruction), LireRegistrePP()); + EcrireRegistrePP(AdditionNonSigne(LireRegistrePP(), 1)); + break; + } + case 127:{ /* HALT-RESET */ + if (ValeurBit(Extension(instruction), 0)) + getc(stdin); /* Halt */ + else + Initialisation(); /* Reset */ + break; + } + default:{ + printf("soja"); + } + } + } +} +void Traitement(void) +{ + Uint32 instruction; + + while (!0) { + instruction = LireInstruction(); + Decode(instruction); + IncrementeCompteurOrdinal(); + } +} + +void Debogueur(void) // transformer en affiche reg +{ + int i,j; + +/* gotoxy(1, 1); + printf("Etat des registres classiques Etat des registres"); + gotoxy(1, 2); + printf(" speciaux "); + gotoxy(1, 11); + printf(" Instruction a decoder"); + gotoxy(1, 14); + printf(" Prochaine instruction"); + for (i = 1; i <= 16; i++) { + gotoxy(1, i + 2); + printf("r%2d:%9d", i - 1, registre[i - 1]); + } + for (i = 17; i <= 32; i++) { + gotoxy(17, i - 16 + 2); + printf("r%2d:%9d", i - 1, registre[i - 1]); + } + gotoxy(40, 4); + printf("Rg :%9d", LireRegistreRG()); + gotoxy(40, 5); + printf("Rd :%9d", LireRegistreRD()); + gotoxy(40, 6); + printf("PC :%9d", LireRegistrePC()); + gotoxy(40, 7); + printf("Flag :%9d", LireRegistreFLAG()); + gotoxy(40, 12); + printf(" %9d", LireInstruction()); + registre[REG_PC]++; + gotoxy(40, 15); + printf(" %9d", LireInstruction()); + registre[REG_PC]--; + getc(stdin); +*/ + for (i=0; i<=3; i++) { + for (j=1; j<=8;j++) { + printf(" R%02d ", (i*8+j)); + } + printf("\n"); + for (j=1; j<=8;j++) { + printf("%08lX ", (registre[i*8+j-1])); + } + printf("\n"); + + } + printf("Rg: %08lX | Rd: %08lX | Flag: %08lX | PC: %08lX\n", LireRegistreRG(), LireRegistreRD(), LireRegistreFLAG(),registre[REG_PC]); + printf("\n"); +} + diff --git a/po/POTFILES.in b/po/POTFILES.in index 9bc5c82..3fb24ac 100644 --- a/po/POTFILES.in +++ b/po/POTFILES.in @@ -6,7 +6,7 @@ lib/parser.c lib/exceptions.c lib/interne.c lib/alu.c -lib/archi.c +lib/simulator.c lib/fpu.c lib/memoire.c lib/registre.c diff --git a/po/ProjetArchi.pot b/po/ProjetArchi.pot index 8dcaa2c..b282c5a 100644 --- a/po/ProjetArchi.pot +++ b/po/ProjetArchi.pot @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2001-04-15 05:17+0200\n" +"POT-Creation-Date: 2001-04-15 13:12+0200\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" -- cgit v1.2.3