From 03638eaea432ac06456cded2cb743d20664689a7 Mon Sep 17 00:00:00 2001 From: Pixel Date: Wed, 26 Jan 2011 23:50:29 -0800 Subject: More senseful init sequence, and memory alignment. --- arch/arm/lpc17xx/ldscript | 7 ++++--- arch/arm/lpc17xx/startup.s | 10 +++------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/arm/lpc17xx/ldscript b/arch/arm/lpc17xx/ldscript index 677d063..14fe819 100644 --- a/arch/arm/lpc17xx/ldscript +++ b/arch/arm/lpc17xx/ldscript @@ -172,23 +172,24 @@ SECTIONS *(.shdata) *(.data .data.* .gnu.linkonce.d.*) *(.ram) - . = ALIGN (8); + . = ALIGN (32); _edata = .; } >ram AT>rom .data_end : { - . = ALIGN(8); + . = ALIGN(32); __rom_data_end = .; } > rom .bss : { + . = ALIGN(32); __bss_ram_begin = .; *(.shbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) *(.ram.b) - . = ALIGN (8); + . = ALIGN(32); __bss_ram_end = .; _end = .; __end = .; diff --git a/arch/arm/lpc17xx/startup.s b/arch/arm/lpc17xx/startup.s index c09971e..a57954a 100644 --- a/arch/arm/lpc17xx/startup.s +++ b/arch/arm/lpc17xx/startup.s @@ -145,13 +145,9 @@ __cs3_reset_cortex_m: LDR R2, =__bss_ram_len BL memset - LDR R0, =lpc17xx_deinit_all - BLX R0 - - LDR R0, =SystemInit - BLX R0 - LDR R0,=_start - BX R0 + BL lpc17xx_deinit_all + BL SystemInit + B _start .pool .cantunwind .fnend -- cgit v1.2.3