From e4e7b661172477aaa682a9cccfbac89adb1d01f6 Mon Sep 17 00:00:00 2001 From: Pixel Date: Sun, 23 Jan 2011 12:15:41 -0800 Subject: Adding basic CMSIS source code; v1.3.0 from the NXP website currently. --- arch/arm/lpc17xx/Drivers/include/debug_frmwrk.h | 69 + arch/arm/lpc17xx/Drivers/include/lpc17xx_adc.h | 288 +++ arch/arm/lpc17xx/Drivers/include/lpc17xx_can.h | 860 +++++++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_clkpwr.h | 394 ++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_dac.h | 142 ++ arch/arm/lpc17xx/Drivers/include/lpc17xx_emac.h | 699 ++++++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_exti.h | 143 ++ arch/arm/lpc17xx/Drivers/include/lpc17xx_gpdma.h | 417 +++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_gpio.h | 165 ++ arch/arm/lpc17xx/Drivers/include/lpc17xx_i2c.h | 377 ++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_i2s.h | 372 ++++ .../Drivers/include/lpc17xx_libcfg_default.h | 170 ++ arch/arm/lpc17xx/Drivers/include/lpc17xx_mcpwm.h | 317 ++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_nvic.h | 64 + arch/arm/lpc17xx/Drivers/include/lpc17xx_pinsel.h | 191 ++ arch/arm/lpc17xx/Drivers/include/lpc17xx_pwm.h | 330 ++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_qei.h | 412 +++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_rit.h | 100 ++ arch/arm/lpc17xx/Drivers/include/lpc17xx_rtc.h | 302 ++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_spi.h | 316 ++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_ssp.h | 460 +++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_systick.h | 107 ++ arch/arm/lpc17xx/Drivers/include/lpc17xx_timer.h | 335 ++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_uart.h | 644 +++++++ arch/arm/lpc17xx/Drivers/include/lpc17xx_wdt.h | 142 ++ arch/arm/lpc17xx/Drivers/include/lpc_types.h | 196 ++ arch/arm/lpc17xx/Drivers/source/debug_frmwrk.c | 305 ++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_adc.c | 340 ++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_can.c | 1891 ++++++++++++++++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_clkpwr.c | 338 ++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_dac.c | 139 ++ arch/arm/lpc17xx/Drivers/source/lpc17xx_emac.c | 950 ++++++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_exti.c | 158 ++ arch/arm/lpc17xx/Drivers/source/lpc17xx_gpdma.c | 450 +++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_gpio.c | 749 ++++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_i2c.c | 1373 ++++++++++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_i2s.c | 642 +++++++ .../Drivers/source/lpc17xx_libcfg_default.c | 64 + arch/arm/lpc17xx/Drivers/source/lpc17xx_mcpwm.c | 497 +++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_nvic.c | 136 ++ arch/arm/lpc17xx/Drivers/source/lpc17xx_pinsel.c | 306 ++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_pwm.c | 533 ++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_qei.c | 502 ++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_rit.c | 187 ++ arch/arm/lpc17xx/Drivers/source/lpc17xx_rtc.c | 771 ++++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_spi.c | 431 +++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_ssp.c | 682 +++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_systick.c | 180 ++ arch/arm/lpc17xx/Drivers/source/lpc17xx_timer.c | 591 ++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_uart.c | 1366 ++++++++++++++ arch/arm/lpc17xx/Drivers/source/lpc17xx_wdt.c | 261 +++ arch/arm/lpc17xx/Drivers/source/makefile | 84 + 52 files changed, 21938 insertions(+) create mode 100644 arch/arm/lpc17xx/Drivers/include/debug_frmwrk.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_adc.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_can.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_clkpwr.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_dac.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_emac.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_exti.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_gpdma.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_gpio.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_i2c.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_i2s.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_libcfg_default.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_mcpwm.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_nvic.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_pinsel.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_pwm.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_qei.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_rit.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_rtc.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_spi.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_ssp.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_systick.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_timer.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_uart.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc17xx_wdt.h create mode 100644 arch/arm/lpc17xx/Drivers/include/lpc_types.h create mode 100644 arch/arm/lpc17xx/Drivers/source/debug_frmwrk.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_adc.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_can.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_clkpwr.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_dac.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_emac.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_exti.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_gpdma.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_gpio.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_i2c.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_i2s.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_libcfg_default.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_mcpwm.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_nvic.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_pinsel.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_pwm.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_qei.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_rit.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_rtc.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_spi.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_ssp.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_systick.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_timer.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_uart.c create mode 100644 arch/arm/lpc17xx/Drivers/source/lpc17xx_wdt.c create mode 100644 arch/arm/lpc17xx/Drivers/source/makefile (limited to 'arch/arm/lpc17xx/Drivers') diff --git a/arch/arm/lpc17xx/Drivers/include/debug_frmwrk.h b/arch/arm/lpc17xx/Drivers/include/debug_frmwrk.h new file mode 100644 index 0000000..b7b56f8 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/debug_frmwrk.h @@ -0,0 +1,69 @@ +/***********************************************************************//** + * @file debug_frmwrk.h + * @brief Contains some utilities that used for debugging through UART + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + *---------------------------------------------------------------------------- + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **********************************************************************/ + +#ifndef DEBUG_FRMWRK_H_ +#define DEBUG_FRMWRK_H_ + +//#include +#include "lpc17xx_uart.h" + +#define USED_UART_DEBUG_PORT 0 + +#if (USED_UART_DEBUG_PORT==0) +#define DEBUG_UART_PORT LPC_UART0 +#elif (USED_UART_DEBUG_PORT==1) +#define DEBUG_UART_PORT LPC_UART1 +#endif + +#define _DBG(x) _db_msg(DEBUG_UART_PORT, x) +#define _DBG_(x) _db_msg_(DEBUG_UART_PORT, x) +#define _DBC(x) _db_char(DEBUG_UART_PORT, x) +#define _DBD(x) _db_dec(DEBUG_UART_PORT, x) +#define _DBD16(x) _db_dec_16(DEBUG_UART_PORT, x) +#define _DBD32(x) _db_dec_32(DEBUG_UART_PORT, x) +#define _DBH(x) _db_hex(DEBUG_UART_PORT, x) +#define _DBH16(x) _db_hex_16(DEBUG_UART_PORT, x) +#define _DBH32(x) _db_hex_32(DEBUG_UART_PORT, x) +#define _DG _db_get_char(DEBUG_UART_PORT) +//void _printf (const char *format, ...); + +extern void (*_db_msg)(LPC_UART_TypeDef *UARTx, const void *s); +extern void (*_db_msg_)(LPC_UART_TypeDef *UARTx, const void *s); +extern void (*_db_char)(LPC_UART_TypeDef *UARTx, uint8_t ch); +extern void (*_db_dec)(LPC_UART_TypeDef *UARTx, uint8_t decn); +extern void (*_db_dec_16)(LPC_UART_TypeDef *UARTx, uint16_t decn); +extern void (*_db_dec_32)(LPC_UART_TypeDef *UARTx, uint32_t decn); +extern void (*_db_hex)(LPC_UART_TypeDef *UARTx, uint8_t hexn); +extern void (*_db_hex_16)(LPC_UART_TypeDef *UARTx, uint16_t hexn); +extern void (*_db_hex_32)(LPC_UART_TypeDef *UARTx, uint32_t hexn); +extern uint8_t (*_db_get_char)(LPC_UART_TypeDef *UARTx); + +void UARTPutChar (LPC_UART_TypeDef *UARTx, uint8_t ch); +void UARTPuts(LPC_UART_TypeDef *UARTx, const void *str); +void UARTPuts_(LPC_UART_TypeDef *UARTx, const void *str); +void UARTPutDec(LPC_UART_TypeDef *UARTx, uint8_t decnum); +void UARTPutDec16(LPC_UART_TypeDef *UARTx, uint16_t decnum); +void UARTPutDec32(LPC_UART_TypeDef *UARTx, uint32_t decnum); +void UARTPutHex (LPC_UART_TypeDef *UARTx, uint8_t hexnum); +void UARTPutHex16 (LPC_UART_TypeDef *UARTx, uint16_t hexnum); +void UARTPutHex32 (LPC_UART_TypeDef *UARTx, uint32_t hexnum); +uint8_t UARTGetChar (LPC_UART_TypeDef *UARTx); +void debug_frmwrk_init(void); + +#endif /* DEBUG_FRMWRK_H_ */ diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_adc.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_adc.h new file mode 100644 index 0000000..377dd7c --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_adc.h @@ -0,0 +1,288 @@ +/***********************************************************************//** + * @file lpc17xx_adc.h + * @brief Contains all macro definitions and function prototypes + * support for ADC firmware library on LPC17xx + * @version 3.0 + * @date 18. June. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup ADC ADC + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_ADC_H_ +#define LPC17XX_ADC_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "LPC17xx.h" +#include "lpc_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Private macros ------------------------------------------------------------- */ +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ + +/* -------------------------- BIT DEFINITIONS ----------------------------------- */ +/*********************************************************************//** + * Macro defines for ADC control register + **********************************************************************/ +/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */ +#define ADC_CR_CH_SEL(n) ((1UL << n)) +/** The APB clock (PCLK) is divided by (this value plus one) +* to produce the clock for the A/D */ +#define ADC_CR_CLKDIV(n) ((n<<8)) +/** Repeated conversions A/D enable bit */ +#define ADC_CR_BURST ((1UL<<16)) +/** ADC convert in power down mode */ +#define ADC_CR_PDN ((1UL<<21)) +/** Start mask bits */ +#define ADC_CR_START_MASK ((7UL<<24)) +/** Select Start Mode */ +#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24)) +/** Start conversion now */ +#define ADC_CR_START_NOW ((1UL<<24)) +/** Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */ +#define ADC_CR_START_EINT0 ((2UL<<24)) +/** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */ +#define ADC_CR_START_CAP01 ((3UL<<24)) +/** Start conversion when the edge selected by bit 27 occurs on MAT0.1 */ +#define ADC_CR_START_MAT01 ((4UL<<24)) +/** Start conversion when the edge selected by bit 27 occurs on MAT0.3 */ +#define ADC_CR_START_MAT03 ((5UL<<24)) +/** Start conversion when the edge selected by bit 27 occurs on MAT1.0 */ +#define ADC_CR_START_MAT10 ((6UL<<24)) +/** Start conversion when the edge selected by bit 27 occurs on MAT1.1 */ +#define ADC_CR_START_MAT11 ((7UL<<24)) +/** Start conversion on a falling edge on the selected CAP/MAT signal */ +#define ADC_CR_EDGE ((1UL<<27)) + +/*********************************************************************//** + * Macro defines for ADC Global Data register + **********************************************************************/ +/** When DONE is 1, this field contains result value of ADC conversion */ +#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF)) +/** These bits contain the channel from which the LS bits were converted */ +#define ADC_GDR_CH(n) (((n>>24)&0x7)) +/** This bit is 1 in burst mode if the results of one or + * more conversions was (were) lost */ +#define ADC_GDR_OVERRUN_FLAG ((1UL<<30)) +/** This bit is set to 1 when an A/D conversion completes */ +#define ADC_GDR_DONE_FLAG ((1UL<<31)) + +/** This bits is used to mask for Channel */ +#define ADC_GDR_CH_MASK ((7UL<<24)) +/*********************************************************************//** + * Macro defines for ADC Interrupt register + **********************************************************************/ +/** These bits allow control over which A/D channels generate + * interrupts for conversion completion */ +#define ADC_INTEN_CH(n) ((1UL<>4)&0xFFF)) +/** These bits mirror the OVERRRUN status flags that appear in the + * result register for each A/D channel */ +#define ADC_DR_OVERRUN_FLAG ((1UL<<30)) +/** This bit is set to 1 when an A/D conversion completes. It is cleared + * when this register is read */ +#define ADC_DR_DONE_FLAG ((1UL<<31)) + +/*********************************************************************//** + * Macro defines for ADC Status register +**********************************************************************/ +/** These bits mirror the DONE status flags that appear in the result + * register for each A/D channel */ +#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF)) +/** These bits mirror the OVERRRUN status flags that appear in the + * result register for each A/D channel */ +#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF)) +/** This bit is the A/D interrupt flag */ +#define ADC_STAT_INT_FLAG ((1UL<<16)) + +/*********************************************************************//** + * Macro defines for ADC Trim register +**********************************************************************/ +/** Offset trim bits for ADC operation */ +#define ADC_ADCOFFS(n) (((n&0xF)<<4)) +/** Written to boot code*/ +#define ADC_TRIM(n) (((n&0xF)<<8)) + +/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */ +/** Check ADC parameter */ +#define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC)) + +/** Check ADC state parameter */ +#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING)) + +/** Check ADC state parameter */ +#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE)) + +/** Check ADC rate parameter */ +#define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000)) + +/** Check ADC channel selection parameter */ +#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\ +||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\ +||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\ +||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7)) + +/** Check ADC start option parameter */ +#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\ +||(OPT == ADC_START_ON_EINT0)||(OPT == ADC_START_ON_CAP01)\ +||(OPT == ADC_START_ON_MAT01)||(OPT == ADC_START_ON_MAT03)\ +||(OPT == ADC_START_ON_MAT10)||(OPT == ADC_START_ON_MAT11)) + +/** Check ADC interrupt type parameter */ +#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\ +||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\ +||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\ +||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\ +||(OPT == ADC_ADGINTEN)) + +/** + * @} + */ + + +/* Public Types --------------------------------------------------------------- */ +/** @defgroup ADC_Public_Types ADC Public Types + * @{ + */ + +/*********************************************************************//** + * @brief ADC enumeration + **********************************************************************/ +/** @brief Channel Selection */ +typedef enum +{ + ADC_CHANNEL_0 = 0, /*!< Channel 0 */ + ADC_CHANNEL_1, /*!< Channel 1 */ + ADC_CHANNEL_2, /*!< Channel 2 */ + ADC_CHANNEL_3, /*!< Channel 3 */ + ADC_CHANNEL_4, /*!< Channel 4 */ + ADC_CHANNEL_5, /*!< Channel 5 */ + ADC_CHANNEL_6, /*!< Channel 6 */ + ADC_CHANNEL_7 /*!< Channel 7 */ +}ADC_CHANNEL_SELECTION; + +/** @brief Type of start option */ +typedef enum +{ + ADC_START_CONTINUOUS =0, /*!< Continuous mode */ + ADC_START_NOW, /*!< Start conversion now */ + ADC_START_ON_EINT0, /*!< Start conversion when the edge selected + * by bit 27 occurs on P2.10/EINT0 */ + ADC_START_ON_CAP01, /*!< Start conversion when the edge selected + * by bit 27 occurs on P1.27/CAP0.1 */ + ADC_START_ON_MAT01, /*!< Start conversion when the edge selected + * by bit 27 occurs on MAT0.1 */ + ADC_START_ON_MAT03, /*!< Start conversion when the edge selected + * by bit 27 occurs on MAT0.3 */ + ADC_START_ON_MAT10, /*!< Start conversion when the edge selected + * by bit 27 occurs on MAT1.0 */ + ADC_START_ON_MAT11 /*!< Start conversion when the edge selected + * by bit 27 occurs on MAT1.1 */ +} ADC_START_OPT; + + +/** @brief Type of edge when start conversion on the selected CAP/MAT signal */ +typedef enum +{ + ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge + *on the selected CAP/MAT signal */ + ADC_START_ON_FALLING /*!< Start conversion on a falling edge + *on the selected CAP/MAT signal */ +} ADC_START_ON_EDGE_OPT; + +/** @brief* ADC type interrupt enum */ +typedef enum +{ + ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */ + ADC_ADINTEN1, /*!< Interrupt channel 1 */ + ADC_ADINTEN2, /*!< Interrupt channel 2 */ + ADC_ADINTEN3, /*!< Interrupt channel 3 */ + ADC_ADINTEN4, /*!< Interrupt channel 4 */ + ADC_ADINTEN5, /*!< Interrupt channel 5 */ + ADC_ADINTEN6, /*!< Interrupt channel 6 */ + ADC_ADINTEN7, /*!< Interrupt channel 7 */ + ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */ +}ADC_TYPE_INT_OPT; + +/** @brief ADC Data status */ +typedef enum +{ + ADC_DATA_BURST = 0, /*Burst bit*/ + ADC_DATA_DONE /*Done bit*/ +}ADC_DATA_STATUS; + +/** + * @} + */ + + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup ADC_Public_Functions ADC Public Functions + * @{ + */ +/* Init/DeInit ADC peripheral ----------------*/ +void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate); +void ADC_DeInit(LPC_ADC_TypeDef *ADCx); + +/* Enable/Disable ADC functions --------------*/ +void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode); +void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState); + +/* Configure ADC functions -------------------*/ +void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption); +void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState); + +/* Get ADC information functions -------------------*/ +uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel); +FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType); +uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx); +FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType); + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* LPC17XX_ADC_H_ */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */ diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_can.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_can.h new file mode 100644 index 0000000..7da1b12 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_can.h @@ -0,0 +1,860 @@ +/***********************************************************************//** + * @file lpc17xx_can.h + * @brief Contains all macro definitions and function prototypes + * support for CAN firmware library on LPC17xx + * @version 3.0 + * @date 18. June. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup CAN CAN + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_CAN_H_ +#define LPC17XX_CAN_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "LPC17xx.h" +#include "lpc_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public Types --------------------------------------------------------------- */ +/** @defgroup CAN_Public_Macros CAN Public Macros + * @{ + */ +#define MSG_ENABLE ((uint8_t)(0)) +#define MSG_DISABLE ((uint8_t)(1)) +#define CAN1_CTRL ((uint8_t)(0)) +#define CAN2_CTRL ((uint8_t)(1)) +#define PARAM_FULLCAN_IC(n) ((n==FULLCAN_IC0)||(n==FULLCAN_IC1)) +#define ID_11 1 +#define MAX_HW_FULLCAN_OBJ 64 +#define MAX_SW_FULLCAN_OBJ 32 + +/** + * @} + */ + +/* Private Macros ------------------------------------------------------------- */ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +/* --------------------- BIT DEFINITIONS -------------------------------------- */ +/*********************************************************************//** + * Macro defines for CAN Mode Register + **********************************************************************/ +/** CAN Reset mode */ +#define CAN_MOD_RM ((uint32_t)(1)) +/** CAN Listen Only Mode */ +#define CAN_MOD_LOM ((uint32_t)(1<<1)) +/** CAN Self Test mode */ +#define CAN_MOD_STM ((uint32_t)(1<<2)) +/** CAN Transmit Priority mode */ +#define CAN_MOD_TPM ((uint32_t)(1<<3)) +/** CAN Sleep mode */ +#define CAN_MOD_SM ((uint32_t)(1<<4)) +/** CAN Receive Polarity mode */ +#define CAN_MOD_RPM ((uint32_t)(1<<5)) +/** CAN Test mode */ +#define CAN_MOD_TM ((uint32_t)(1<<7)) + +/*********************************************************************//** + * Macro defines for CAN Command Register + **********************************************************************/ +/** CAN Transmission Request */ +#define CAN_CMR_TR ((uint32_t)(1)) +/** CAN Abort Transmission */ +#define CAN_CMR_AT ((uint32_t)(1<<1)) +/** CAN Release Receive Buffer */ +#define CAN_CMR_RRB ((uint32_t)(1<<2)) +/** CAN Clear Data Overrun */ +#define CAN_CMR_CDO ((uint32_t)(1<<3)) +/** CAN Self Reception Request */ +#define CAN_CMR_SRR ((uint32_t)(1<<4)) +/** CAN Select Tx Buffer 1 */ +#define CAN_CMR_STB1 ((uint32_t)(1<<5)) +/** CAN Select Tx Buffer 2 */ +#define CAN_CMR_STB2 ((uint32_t)(1<<6)) +/** CAN Select Tx Buffer 3 */ +#define CAN_CMR_STB3 ((uint32_t)(1<<7)) + +/*********************************************************************//** + * Macro defines for CAN Global Status Register + **********************************************************************/ +/** CAN Receive Buffer Status */ +#define CAN_GSR_RBS ((uint32_t)(1)) +/** CAN Data Overrun Status */ +#define CAN_GSR_DOS ((uint32_t)(1<<1)) +/** CAN Transmit Buffer Status */ +#define CAN_GSR_TBS ((uint32_t)(1<<2)) +/** CAN Transmit Complete Status */ +#define CAN_GSR_TCS ((uint32_t)(1<<3)) +/** CAN Receive Status */ +#define CAN_GSR_RS ((uint32_t)(1<<4)) +/** CAN Transmit Status */ +#define CAN_GSR_TS ((uint32_t)(1<<5)) +/** CAN Error Status */ +#define CAN_GSR_ES ((uint32_t)(1<<6)) +/** CAN Bus Status */ +#define CAN_GSR_BS ((uint32_t)(1<<7)) +/** CAN Current value of the Rx Error Counter */ +#define CAN_GSR_RXERR(n) ((uint32_t)((n&0xFF)<<16)) +/** CAN Current value of the Tx Error Counter */ +#define CAN_GSR_TXERR(n) ((uint32_t)(n&0xFF)<<24)) + +/*********************************************************************//** + * Macro defines for CAN Interrupt and Capture Register + **********************************************************************/ +/** CAN Receive Interrupt */ +#define CAN_ICR_RI ((uint32_t)(1)) +/** CAN Transmit Interrupt 1 */ +#define CAN_ICR_TI1 ((uint32_t)(1<<1)) +/** CAN Error Warning Interrupt */ +#define CAN_ICR_EI ((uint32_t)(1<<2)) +/** CAN Data Overrun Interrupt */ +#define CAN_ICR_DOI ((uint32_t)(1<<3)) +/** CAN Wake-Up Interrupt */ +#define CAN_ICR_WUI ((uint32_t)(1<<4)) +/** CAN Error Passive Interrupt */ +#define CAN_ICR_EPI ((uint32_t)(1<<5)) +/** CAN Arbitration Lost Interrupt */ +#define CAN_ICR_ALI ((uint32_t)(1<<6)) +/** CAN Bus Error Interrupt */ +#define CAN_ICR_BEI ((uint32_t)(1<<7)) +/** CAN ID Ready Interrupt */ +#define CAN_ICR_IDI ((uint32_t)(1<<8)) +/** CAN Transmit Interrupt 2 */ +#define CAN_ICR_TI2 ((uint32_t)(1<<9)) +/** CAN Transmit Interrupt 3 */ +#define CAN_ICR_TI3 ((uint32_t)(1<<10)) +/** CAN Error Code Capture */ +#define CAN_ICR_ERRBIT(n) ((uint32_t)((n&0x1F)<<16)) +/** CAN Error Direction */ +#define CAN_ICR_ERRDIR ((uint32_t)(1<<21)) +/** CAN Error Capture */ +#define CAN_ICR_ERRC(n) ((uint32_t)((n&0x3)<<22)) +/** CAN Arbitration Lost Capture */ +#define CAN_ICR_ALCBIT(n) ((uint32_t)((n&0xFF)<<24)) + +/*********************************************************************//** + * Macro defines for CAN Interrupt Enable Register + **********************************************************************/ +/** CAN Receive Interrupt Enable */ +#define CAN_IER_RIE ((uint32_t)(1)) +/** CAN Transmit Interrupt Enable for buffer 1 */ +#define CAN_IER_TIE1 ((uint32_t)(1<<1)) +/** CAN Error Warning Interrupt Enable */ +#define CAN_IER_EIE ((uint32_t)(1<<2)) +/** CAN Data Overrun Interrupt Enable */ +#define CAN_IER_DOIE ((uint32_t)(1<<3)) +/** CAN Wake-Up Interrupt Enable */ +#define CAN_IER_WUIE ((uint32_t)(1<<4)) +/** CAN Error Passive Interrupt Enable */ +#define CAN_IER_EPIE ((uint32_t)(1<<5)) +/** CAN Arbitration Lost Interrupt Enable */ +#define CAN_IER_ALIE ((uint32_t)(1<<6)) +/** CAN Bus Error Interrupt Enable */ +#define CAN_IER_BEIE ((uint32_t)(1<<7)) +/** CAN ID Ready Interrupt Enable */ +#define CAN_IER_IDIE ((uint32_t)(1<<8)) +/** CAN Transmit Enable Interrupt for Buffer 2 */ +#define CAN_IER_TIE2 ((uint32_t)(1<<9)) +/** CAN Transmit Enable Interrupt for Buffer 3 */ +#define CAN_IER_TIE3 ((uint32_t)(1<<10)) + +/*********************************************************************//** + * Macro defines for CAN Bus Timing Register + **********************************************************************/ +/** CAN Baudrate Prescaler */ +#define CAN_BTR_BRP(n) ((uint32_t)(n&0x3FF)) +/** CAN Synchronization Jump Width */ +#define CAN_BTR_SJM(n) ((uint32_t)((n&0x3)<<14)) +/** CAN Time Segment 1 */ +#define CAN_BTR_TESG1(n) ((uint32_t)(n&0xF)<<16)) +/** CAN Time Segment 2 */ +#define CAN_BTR_TESG2(n) ((uint32_t)(n&0xF)<<20)) +/** CAN Sampling */ +#define CAN_BTR_SAM(n) ((uint32_t)(1<<23)) + +/*********************************************************************//** + * Macro defines for CAN Error Warning Limit Register + **********************************************************************/ +/** CAN Error Warning Limit */ +#define CAN_EWL_EWL(n) ((uint32_t)(n&0xFF)) + +/*********************************************************************//** + * Macro defines for CAN Status Register + **********************************************************************/ +/** CAN Receive Buffer Status */ +#define CAN_SR_RBS ((uint32_t)(1)) +/** CAN Data Overrun Status */ +#define CAN_SR_DOS ((uint32_t)(1<<1)) +/** CAN Transmit Buffer Status 1 */ +#define CAN_SR_TBS1 ((uint32_t)(1<<2)) +/** CAN Transmission Complete Status of Buffer 1 */ +#define CAN_SR_TCS1 ((uint32_t)(1<<3)) +/** CAN Receive Status */ +#define CAN_SR_RS ((uint32_t)(1<<4)) +/** CAN Transmit Status 1 */ +#define CAN_SR_TS1 ((uint32_t)(1<<5)) +/** CAN Error Status */ +#define CAN_SR_ES ((uint32_t)(1<<6)) +/** CAN Bus Status */ +#define CAN_SR_BS ((uint32_t)(1<<7)) +/** CAN Transmit Buffer Status 2 */ +#define CAN_SR_TBS2 ((uint32_t)(1<<10)) +/** CAN Transmission Complete Status of Buffer 2 */ +#define CAN_SR_TCS2 ((uint32_t)(1<<11)) +/** CAN Transmit Status 2 */ +#define CAN_SR_TS2 ((uint32_t)(1<<13)) +/** CAN Transmit Buffer Status 2 */ +#define CAN_SR_TBS3 ((uint32_t)(1<<18)) +/** CAN Transmission Complete Status of Buffer 2 */ +#define CAN_SR_TCS3 ((uint32_t)(1<<19)) +/** CAN Transmit Status 2 */ +#define CAN_SR_TS3 ((uint32_t)(1<<21)) + +/*********************************************************************//** + * Macro defines for CAN Receive Frame Status Register + **********************************************************************/ +/** CAN ID Index */ +#define CAN_RFS_ID_INDEX(n) ((uint32_t)(n&0x3FF)) +/** CAN Bypass */ +#define CAN_RFS_BP ((uint32_t)(1<<10)) +/** CAN Data Length Code */ +#define CAN_RFS_DLC(n) ((uint32_t)((n&0xF)<<16) +/** CAN Remote Transmission Request */ +#define CAN_RFS_RTR ((uint32_t)(1<<30)) +/** CAN control 11 bit or 29 bit Identifier */ +#define CAN_RFS_FF ((uint32_t)(1<<31)) + +/*********************************************************************//** + * Macro defines for CAN Receive Identifier Register + **********************************************************************/ +/** CAN 11 bit Identifier */ +#define CAN_RID_ID_11(n) ((uint32_t)(n&0x7FF)) +/** CAN 29 bit Identifier */ +#define CAN_RID_ID_29(n) ((uint32_t)(n&0x1FFFFFFF)) + +/*********************************************************************//** + * Macro defines for CAN Receive Data A Register + **********************************************************************/ +/** CAN Receive Data 1 */ +#define CAN_RDA_DATA1(n) ((uint32_t)(n&0xFF)) +/** CAN Receive Data 2 */ +#define CAN_RDA_DATA2(n) ((uint32_t)((n&0xFF)<<8)) +/** CAN Receive Data 3 */ +#define CAN_RDA_DATA3(n) ((uint32_t)((n&0xFF)<<16)) +/** CAN Receive Data 4 */ +#define CAN_RDA_DATA4(n) ((uint32_t)((n&0xFF)<<24)) + +/*********************************************************************//** + * Macro defines for CAN Receive Data B Register + **********************************************************************/ +/** CAN Receive Data 5 */ +#define CAN_RDB_DATA5(n) ((uint32_t)(n&0xFF)) +/** CAN Receive Data 6 */ +#define CAN_RDB_DATA6(n) ((uint32_t)((n&0xFF)<<8)) +/** CAN Receive Data 7 */ +#define CAN_RDB_DATA7(n) ((uint32_t)((n&0xFF)<<16)) +/** CAN Receive Data 8 */ +#define CAN_RDB_DATA8(n) ((uint32_t)((n&0xFF)<<24)) + +/*********************************************************************//** + * Macro defines for CAN Transmit Frame Information Register + **********************************************************************/ +/** CAN Priority */ +#define CAN_TFI_PRIO(n) ((uint32_t)(n&0xFF)) +/** CAN Data Length Code */ +#define CAN_TFI_DLC(n) ((uint32_t)((n&0xF)<<16)) +/** CAN Remote Frame Transmission */ +#define CAN_TFI_RTR ((uint32_t)(1<<30)) +/** CAN control 11-bit or 29-bit Identifier */ +#define CAN_TFI_FF ((uint32_t)(1<<31)) + +/*********************************************************************//** + * Macro defines for CAN Transmit Identifier Register + **********************************************************************/ +/** CAN 11-bit Identifier */ +#define CAN_TID_ID11(n) ((uint32_t)(n&0x7FF)) +/** CAN 11-bit Identifier */ +#define CAN_TID_ID29(n) ((uint32_t)(n&0x1FFFFFFF)) + +/*********************************************************************//** + * Macro defines for CAN Transmit Data A Register + **********************************************************************/ +/** CAN Transmit Data 1 */ +#define CAN_TDA_DATA1(n) ((uint32_t)(n&0xFF)) +/** CAN Transmit Data 2 */ +#define CAN_TDA_DATA2(n) ((uint32_t)((n&0xFF)<<8)) +/** CAN Transmit Data 3 */ +#define CAN_TDA_DATA3(n) ((uint32_t)((n&0xFF)<<16)) +/** CAN Transmit Data 4 */ +#define CAN_TDA_DATA4(n) ((uint32_t)((n&0xFF)<<24)) + +/*********************************************************************//** + * Macro defines for CAN Transmit Data B Register + **********************************************************************/ +/** CAN Transmit Data 5 */ +#define CAN_TDA_DATA5(n) ((uint32_t)(n&0xFF)) +/** CAN Transmit Data 6 */ +#define CAN_TDA_DATA6(n) ((uint32_t)((n&0xFF)<<8)) +/** CAN Transmit Data 7 */ +#define CAN_TDA_DATA7(n) ((uint32_t)((n&0xFF)<<16)) +/** CAN Transmit Data 8 */ +#define CAN_TDA_DATA8(n) ((uint32_t)((n&0xFF)<<24)) + +/*********************************************************************//** + * Macro defines for CAN Sleep Clear Register + **********************************************************************/ +/** CAN1 Sleep mode */ +#define CAN1SLEEPCLR ((uint32_t)(1<<1)) +/** CAN2 Sleep Mode */ +#define CAN2SLEEPCLR ((uint32_t)(1<<2)) + +/*********************************************************************//** + * Macro defines for CAN Wake up Flags Register + **********************************************************************/ +/** CAN1 Sleep mode */ +#define CAN_WAKEFLAGES_CAN1WAKE ((uint32_t)(1<<1)) +/** CAN2 Sleep Mode */ +#define CAN_WAKEFLAGES_CAN2WAKE ((uint32_t)(1<<2)) + +/*********************************************************************//** + * Macro defines for Central transmit Status Register + **********************************************************************/ +/** CAN Transmit 1 */ +#define CAN_TSR_TS1 ((uint32_t)(1)) +/** CAN Transmit 2 */ +#define CAN_TSR_TS2 ((uint32_t)(1<<1)) +/** CAN Transmit Buffer Status 1 */ +#define CAN_TSR_TBS1 ((uint32_t)(1<<8)) +/** CAN Transmit Buffer Status 2 */ +#define CAN_TSR_TBS2 ((uint32_t)(1<<9)) +/** CAN Transmission Complete Status 1 */ +#define CAN_TSR_TCS1 ((uint32_t)(1<<16)) +/** CAN Transmission Complete Status 2 */ +#define CAN_TSR_TCS2 ((uint32_t)(1<<17)) + +/*********************************************************************//** + * Macro defines for Central Receive Status Register + **********************************************************************/ +/** CAN Receive Status 1 */ +#define CAN_RSR_RS1 ((uint32_t)(1)) +/** CAN Receive Status 1 */ +#define CAN_RSR_RS2 ((uint32_t)(1<<1)) +/** CAN Receive Buffer Status 1*/ +#define CAN_RSR_RB1 ((uint32_t)(1<<8)) +/** CAN Receive Buffer Status 2*/ +#define CAN_RSR_RB2 ((uint32_t)(1<<9)) +/** CAN Data Overrun Status 1 */ +#define CAN_RSR_DOS1 ((uint32_t)(1<<16)) +/** CAN Data Overrun Status 1 */ +#define CAN_RSR_DOS2 ((uint32_t)(1<<17)) + +/*********************************************************************//** + * Macro defines for Central Miscellaneous Status Register + **********************************************************************/ +/** Same CAN Error Status in CAN1GSR */ +#define CAN_MSR_E1 ((uint32_t)(1)) +/** Same CAN Error Status in CAN2GSR */ +#define CAN_MSR_E2 ((uint32_t)(1<<1)) +/** Same CAN Bus Status in CAN1GSR */ +#define CAN_MSR_BS1 ((uint32_t)(1<<8)) +/** Same CAN Bus Status in CAN2GSR */ +#define CAN_MSR_BS2 ((uint32_t)(1<<9)) + +/*********************************************************************//** + * Macro defines for Acceptance Filter Mode Register + **********************************************************************/ +/** CAN Acceptance Filter Off mode */ +#define CAN_AFMR_AccOff ((uint32_t)(1)) +/** CAN Acceptance File Bypass mode */ +#define CAN_AFMR_AccBP ((uint32_t)(1<<1)) +/** FullCAN Mode Enhancements */ +#define CAN_AFMR_eFCAN ((uint32_t)(1<<2)) + +/*********************************************************************//** + * Macro defines for Standard Frame Individual Start Address Register + **********************************************************************/ +/** The start address of the table of individual Standard Identifier */ +#define CAN_STT_sa(n) ((uint32_t)((n&1FF)<<2)) + +/*********************************************************************//** + * Macro defines for Standard Frame Group Start Address Register + **********************************************************************/ +/** The start address of the table of grouped Standard Identifier */ +#define CAN_SFF_GRP_sa(n) ((uint32_t)((n&3FF)<<2)) + +/*********************************************************************//** + * Macro defines for Extended Frame Start Address Register + **********************************************************************/ +/** The start address of the table of individual Extended Identifier */ +#define CAN_EFF_sa(n) ((uint32_t)((n&1FF)<<2)) + +/*********************************************************************//** + * Macro defines for Extended Frame Group Start Address Register + **********************************************************************/ +/** The start address of the table of grouped Extended Identifier */ +#define CAN_Eff_GRP_sa(n) ((uint32_t)((n&3FF)<<2)) + +/*********************************************************************//** + * Macro defines for End Of AF Table Register + **********************************************************************/ +/** The End of Table of AF LookUp Table */ +#define CAN_EndofTable(n) ((uint32_t)((n&3FF)<<2)) + +/*********************************************************************//** + * Macro defines for LUT Error Address Register + **********************************************************************/ +/** CAN Look-Up Table Error Address */ +#define CAN_LUTerrAd(n) ((uint32_t)((n&1FF)<<2)) + +/*********************************************************************//** + * Macro defines for LUT Error Register + **********************************************************************/ +/** CAN Look-Up Table Error */ +#define CAN_LUTerr ((uint32_t)(1)) + +/*********************************************************************//** + * Macro defines for Global FullCANInterrupt Enable Register + **********************************************************************/ +/** Global FullCANInterrupt Enable */ +#define CAN_FCANIE ((uint32_t)(1)) + +/*********************************************************************//** + * Macro defines for FullCAN Interrupt and Capture Register 0 + **********************************************************************/ +/** FullCAN Interrupt and Capture (0-31)*/ +#define CAN_FCANIC0_IntPnd(n) ((uint32_t)(1<=0)&&(data <= 0xFFFFFFFF)) + +/** Macro to check frequency value */ +#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000)) + +/** Macro to check Frame Identifier */ +#define PARAM_ID_11(n) ((n>>11)==0) /*-- 11 bit --*/ +#define PARAM_ID_29(n) ((n>>29)==0) /*-- 29 bit --*/ + +/** Macro to check DLC value */ +#define PARAM_DLC(n) ((n>>4)==0) /*-- 4 bit --*/ +/** Macro to check ID format type */ +#define PARAM_ID_FORMAT(n) ((n==STD_ID_FORMAT)||(n==EXT_ID_FORMAT)) + +/** Macro to check Group identifier */ +#define PARAM_GRP_ID(x, y) ((x<=y)) + +/** Macro to check Frame type */ +#define PARAM_FRAME_TYPE(n) ((n==DATA_FRAME)||(n==REMOTE_FRAME)) + +/** Macro to check Control/Central Status type parameter */ +#define PARAM_CTRL_STS_TYPE(n) ((n==CANCTRL_GLOBAL_STS)||(n==CANCTRL_INT_CAP) \ +||(n==CANCTRL_ERR_WRN)||(n==CANCTRL_STS)) + +/** Macro to check CR status type */ +#define PARAM_CR_STS_TYPE(n) ((n==CANCR_TX_STS)||(n==CANCR_RX_STS) \ +||(n==CANCR_MS)) +/** Macro to check AF Mode type parameter */ +#define PARAM_AFMODE_TYPE(n) ((n==CAN_Normal)||(n==CAN_AccOff) \ +||(n==CAN_AccBP)||(n==CAN_eFCAN)) + +/** Macro to check Operation Mode */ +#define PARAM_MODE_TYPE(n) ((n==CAN_OPERATING_MODE)||(n==CAN_RESET_MODE) \ +||(n==CAN_LISTENONLY_MODE)||(n==CAN_SELFTEST_MODE) \ +||(n==CAN_TXPRIORITY_MODE)||(n==CAN_SLEEP_MODE) \ +||(n==CAN_RXPOLARITY_MODE)||(n==CAN_TEST_MODE)) + +/** Macro define for struct AF_Section parameter */ +#define PARAM_CTRL(n) ((n==CAN1_CTRL)|(n==CAN2_CTRL)) + +/** Macro define for struct AF_Section parameter */ +#define PARAM_MSG_DISABLE(n) ((n==MSG_ENABLE)|(n==MSG_DISABLE)) + +/**Macro to check Interrupt Type parameter */ +#define PARAM_INT_EN_TYPE(n) ((n==CANINT_RIE)||(n==CANINT_TIE1) \ +||(n==CANINT_EIE)||(n==CANINT_DOIE) \ +||(n==CANINT_WUIE)||(n==CANINT_EPIE) \ +||(n==CANINT_ALIE)||(n==CANINT_BEIE) \ +||(n==CANINT_IDIE)||(n==CANINT_TIE2) \ +||(n==CANINT_TIE3)||(n==CANINT_FCE)) + +/** Macro to check AFLUT Entry type */ +#define PARAM_AFLUT_ENTRY_TYPE(n) ((n==FULLCAN_ENTRY)||(n==EXPLICIT_STANDARD_ENTRY)\ +||(n==GROUP_STANDARD_ENTRY)||(n==EXPLICIT_EXTEND_ENTRY) \ +||(n==GROUP_EXTEND_ENTRY)) + +/** Macro to check position */ +#define PARAM_POSITION(n) ((n>=0)&&(n<512)) + +/** + * @} + */ + +/* Public Types --------------------------------------------------------------- */ +/** @defgroup CAN_Public_Types CAN Public Types + * @{ + */ + +/** CAN configuration structure */ +/*********************************************************************** + * CAN device configuration commands (IOCTL commands and arguments) + **********************************************************************/ +/** + * @brief CAN ID format definition + */ +typedef enum { + STD_ID_FORMAT = 0, /**< Use standard ID format (11 bit ID) */ + EXT_ID_FORMAT = 1 /**< Use extended ID format (29 bit ID) */ +} CAN_ID_FORMAT_Type; + +/** + * @brief AFLUT Entry type definition + */ +typedef enum { + FULLCAN_ENTRY = 0, + EXPLICIT_STANDARD_ENTRY, + GROUP_STANDARD_ENTRY, + EXPLICIT_EXTEND_ENTRY, + GROUP_EXTEND_ENTRY, +} AFLUT_ENTRY_Type; + +/** + * @brief Symbolic names for type of CAN message + */ +typedef enum { + DATA_FRAME = 0, /**< Data frame */ + REMOTE_FRAME = 1 /**< Remote frame */ +} CAN_FRAME_Type; + +/** + * @brief CAN Control status definition + */ +typedef enum { + CANCTRL_GLOBAL_STS = 0, /**< CAN Global Status */ + CANCTRL_INT_CAP, /**< CAN Interrupt and Capture */ + CANCTRL_ERR_WRN, /**< CAN Error Warning Limit */ + CANCTRL_STS /**< CAN Control Status */ +} CAN_CTRL_STS_Type; + +/** + * @brief Central CAN status type definition + */ +typedef enum { + CANCR_TX_STS = 0, /**< Central CAN Tx Status */ + CANCR_RX_STS, /**< Central CAN Rx Status */ + CANCR_MS /**< Central CAN Miscellaneous Status */ +} CAN_CR_STS_Type; + +/** + * @brief FullCAN Interrupt Capture type definition + */ +typedef enum{ + FULLCAN_IC0, /**< FullCAN Interrupt and Capture 0 */ + FULLCAN_IC1 /**< FullCAN Interrupt and Capture 1 */ +}FullCAN_IC_Type; + +/** + * @brief CAN interrupt enable type definition + */ +typedef enum { + CANINT_RIE = 0, /**< CAN Receiver Interrupt Enable */ + CANINT_TIE1, /**< CAN Transmit Interrupt Enable */ + CANINT_EIE, /**< CAN Error Warning Interrupt Enable */ + CANINT_DOIE, /**< CAN Data Overrun Interrupt Enable */ + CANINT_WUIE, /**< CAN Wake-Up Interrupt Enable */ + CANINT_EPIE, /**< CAN Error Passive Interrupt Enable */ + CANINT_ALIE, /**< CAN Arbitration Lost Interrupt Enable */ + CANINT_BEIE, /**< CAN Bus Error Inter rupt Enable */ + CANINT_IDIE, /**< CAN ID Ready Interrupt Enable */ + CANINT_TIE2, /**< CAN Transmit Interrupt Enable for Buffer2 */ + CANINT_TIE3, /**< CAN Transmit Interrupt Enable for Buffer3 */ + CANINT_FCE /**< FullCAN Interrupt Enable */ +} CAN_INT_EN_Type; + +/** + * @brief Acceptance Filter Mode type definition + */ +typedef enum { + CAN_Normal = 0, /**< Normal Mode */ + CAN_AccOff, /**< Acceptance Filter Off Mode */ + CAN_AccBP, /**< Acceptance Fileter Bypass Mode */ + CAN_eFCAN /**< FullCAN Mode Enhancement */ +} CAN_AFMODE_Type; + +/** + * @brief CAN Mode Type definition + */ +typedef enum { + CAN_OPERATING_MODE = 0, /**< Operating Mode */ + CAN_RESET_MODE, /**< Reset Mode */ + CAN_LISTENONLY_MODE, /**< Listen Only Mode */ + CAN_SELFTEST_MODE, /**< Seft Test Mode */ + CAN_TXPRIORITY_MODE, /**< Transmit Priority Mode */ + CAN_SLEEP_MODE, /**< Sleep Mode */ + CAN_RXPOLARITY_MODE, /**< Receive Polarity Mode */ + CAN_TEST_MODE /**< Test Mode */ +} CAN_MODE_Type; + +/** + * @brief Error values that functions can return + */ +typedef enum { + CAN_OK = 1, /**< No error */ + CAN_OBJECTS_FULL_ERROR, /**< No more rx or tx objects available */ + CAN_FULL_OBJ_NOT_RCV, /**< Full CAN object not received */ + CAN_NO_RECEIVE_DATA, /**< No have receive data available */ + CAN_AF_ENTRY_ERROR, /**< Entry load in AFLUT is unvalid */ + CAN_CONFLICT_ID_ERROR, /**< Conflict ID occur */ + CAN_ENTRY_NOT_EXIT_ERROR /**< Entry remove outo AFLUT is not exit */ +} CAN_ERROR; + +/** + * @brief Pin Configuration structure + */ +typedef struct { + uint8_t RD; /**< Serial Inputs, from CAN transceivers, should be: + ** For CAN1: + - CAN_RD1_P0_0: RD pin is on P0.0 + - CAN_RD1_P0_21 : RD pin is on P0.21 + ** For CAN2: + - CAN_RD2_P0_4: RD pin is on P0.4 + - CAN_RD2_P2_7: RD pin is on P2.7 + */ + uint8_t TD; /**< Serial Outputs, To CAN transceivers, should be: + ** For CAN1: + - CAN_TD1_P0_1: TD pin is on P0.1 + - CAN_TD1_P0_22: TD pin is on P0.22 + ** For CAN2: + - CAN_TD2_P0_5: TD pin is on P0.5 + - CAN_TD2_P2_8: TD pin is on P2.8 + */ +} CAN_PinCFG_Type; + +/** + * @brief CAN message object structure + */ +typedef struct { + uint32_t id; /**< 29 bit identifier, it depend on "format" value + - if format = STD_ID_FORMAT, id should be 11 bit identifier + - if format = EXT_ID_FORMAT, id should be 29 bit identifier + */ + uint8_t dataA[4]; /**< Data field A */ + uint8_t dataB[4]; /**< Data field B */ + uint8_t len; /**< Length of data field in bytes, should be: + - 0000b-0111b: 0-7 bytes + - 1xxxb: 8 bytes + */ + uint8_t format; /**< Identifier Format, should be: + - STD_ID_FORMAT: Standard ID - 11 bit format + - EXT_ID_FORMAT: Extended ID - 29 bit format + */ + uint8_t type; /**< Remote Frame transmission, should be: + - DATA_FRAME: the number of data bytes called out by the DLC + field are send from the CANxTDA and CANxTDB registers + - REMOTE_FRAME: Remote Frame is sent + */ +} CAN_MSG_Type; + +/** + * @brief FullCAN Entry structure + */ +typedef struct { + uint8_t controller; /**< CAN Controller, should be: + - CAN1_CTRL: CAN1 Controller + - CAN2_CTRL: CAN2 Controller + */ + uint8_t disable; /**< Disable bit, should be: + - MSG_ENABLE: disable bit = 0 + - MSG_DISABLE: disable bit = 1 + */ + uint16_t id_11; /**< Standard ID, should be 11-bit value */ +} FullCAN_Entry; + +/** + * @brief Standard ID Frame Format Entry structure + */ +typedef struct { + uint8_t controller; /**< CAN Controller, should be: + - CAN1_CTRL: CAN1 Controller + - CAN2_CTRL: CAN2 Controller + */ + uint8_t disable; /**< Disable bit, should be: + - MSG_ENABLE: disable bit = 0 + - MSG_DISABLE: disable bit = 1 + */ + uint16_t id_11; /**< Standard ID, should be 11-bit value */ +} SFF_Entry; + +/** + * @brief Group of Standard ID Frame Format Entry structure + */ +typedef struct { + uint8_t controller1; /**< First CAN Controller, should be: + - CAN1_CTRL: CAN1 Controller + - CAN2_CTRL: CAN2 Controller + */ + uint8_t disable1; /**< First Disable bit, should be: + - MSG_ENABLE: disable bit = 0) + - MSG_DISABLE: disable bit = 1 + */ + uint16_t lowerID; /**< ID lower bound, should be 11-bit value */ + uint8_t controller2; /**< Second CAN Controller, should be: + - CAN1_CTRL: CAN1 Controller + - CAN2_CTRL: CAN2 Controller + */ + uint8_t disable2; /**< Second Disable bit, should be: + - MSG_ENABLE: disable bit = 0 + - MSG_DISABLE: disable bit = 1 + */ + uint16_t upperID; /**< ID upper bound, should be 11-bit value and + equal or greater than lowerID + */ +} SFF_GPR_Entry; + +/** + * @brief Extended ID Frame Format Entry structure + */ +typedef struct { + uint8_t controller; /**< CAN Controller, should be: + - CAN1_CTRL: CAN1 Controller + - CAN2_CTRL: CAN2 Controller + */ + uint32_t ID_29; /**< Extend ID, shoud be 29-bit value */ +} EFF_Entry; + + +/** + * @brief Group of Extended ID Frame Format Entry structure + */ +typedef struct { + uint8_t controller1; /**< First CAN Controller, should be: + - CAN1_CTRL: CAN1 Controller + - CAN2_CTRL: CAN2 Controller + */ + uint8_t controller2; /**< Second Disable bit, should be: + - MSG_ENABLE: disable bit = 0(default) + - MSG_DISABLE: disable bit = 1 + */ + uint32_t lowerEID; /**< Extended ID lower bound, should be 29-bit value */ + uint32_t upperEID; /**< Extended ID upper bound, should be 29-bit value */ +} EFF_GPR_Entry; + + +/** + * @brief Acceptance Filter Section Table structure + */ +typedef struct { + FullCAN_Entry* FullCAN_Sec; /**< The pointer point to FullCAN_Entry */ + uint8_t FC_NumEntry; /**< FullCAN Entry Number */ + SFF_Entry* SFF_Sec; /**< The pointer point to SFF_Entry */ + uint8_t SFF_NumEntry; /**< Standard ID Entry Number */ + SFF_GPR_Entry* SFF_GPR_Sec; /**< The pointer point to SFF_GPR_Entry */ + uint8_t SFF_GPR_NumEntry; /**< Group Standard ID Entry Number */ + EFF_Entry* EFF_Sec; /**< The pointer point to EFF_Entry */ + uint8_t EFF_NumEntry; /**< Extended ID Entry Number */ + EFF_GPR_Entry* EFF_GPR_Sec; /**< The pointer point to EFF_GPR_Entry */ + uint8_t EFF_GPR_NumEntry; /**< Group Extended ID Entry Number */ +} AF_SectionDef; + +/** + * @} + */ + + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup CAN_Public_Functions CAN Public Functions + * @{ + */ + +/* Init/DeInit CAN peripheral -----------*/ +void CAN_Init(LPC_CAN_TypeDef *CANx, uint32_t baudrate); +void CAN_DeInit(LPC_CAN_TypeDef *CANx); + +/* CAN messages functions ---------------*/ +Status CAN_SendMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg); +Status CAN_ReceiveMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg); +CAN_ERROR FCAN_ReadObj(LPC_CANAF_TypeDef* CANAFx, CAN_MSG_Type *CAN_Msg); + +/* CAN configure functions ---------------*/ +void CAN_ModeConfig(LPC_CAN_TypeDef* CANx, CAN_MODE_Type mode, + FunctionalState NewState); +void CAN_SetAFMode(LPC_CANAF_TypeDef* CANAFx, CAN_AFMODE_Type AFmode); +void CAN_SetCommand(LPC_CAN_TypeDef* CANx, uint32_t CMRType); + +/* AFLUT functions ---------------------- */ +CAN_ERROR CAN_SetupAFLUT(LPC_CANAF_TypeDef* CANAFx, AF_SectionDef* AFSection); +CAN_ERROR CAN_LoadFullCANEntry(LPC_CAN_TypeDef* CANx, uint16_t ID); +CAN_ERROR CAN_LoadExplicitEntry(LPC_CAN_TypeDef* CANx, uint32_t ID, + CAN_ID_FORMAT_Type format); +CAN_ERROR CAN_LoadGroupEntry(LPC_CAN_TypeDef* CANx, uint32_t lowerID, + uint32_t upperID, CAN_ID_FORMAT_Type format); +CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position); + +/* CAN interrupt functions -----------------*/ +void CAN_IRQCmd(LPC_CAN_TypeDef* CANx, CAN_INT_EN_Type arg, FunctionalState NewState); +uint32_t CAN_IntGetStatus(LPC_CAN_TypeDef* CANx); + +/* CAN get status functions ----------------*/ +IntStatus CAN_FullCANIntGetStatus (LPC_CANAF_TypeDef* CANAFx); +uint32_t CAN_FullCANPendGetStatus (LPC_CANAF_TypeDef* CANAFx, FullCAN_IC_Type type); +uint32_t CAN_GetCTRLStatus(LPC_CAN_TypeDef* CANx, CAN_CTRL_STS_Type arg); +uint32_t CAN_GetCRStatus(LPC_CANCR_TypeDef* CANCRx, CAN_CR_STS_Type arg); + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LPC17XX_CAN_H_ */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */ diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_clkpwr.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_clkpwr.h new file mode 100644 index 0000000..b8876e2 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_clkpwr.h @@ -0,0 +1,394 @@ +/***********************************************************************//** + * @file lpc17xx_clkpwr.h + * @brief Contains all macro definitions and function prototypes + * support for Clock and Power Control firmware library on LPC17xx + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup CLKPWR CLKPWR + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_CLKPWR_H_ +#define LPC17XX_CLKPWR_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "lpc17xx.h" +#include "lpc_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public Macros -------------------------------------------------------------- */ +/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros + * @{ + */ + +/********************************************************************** + * Peripheral Clock Selection Definitions + **********************************************************************/ +/** Peripheral clock divider bit position for WDT */ +#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0)) +/** Peripheral clock divider bit position for TIMER0 */ +#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2)) +/** Peripheral clock divider bit position for TIMER1 */ +#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4)) +/** Peripheral clock divider bit position for UART0 */ +#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6)) +/** Peripheral clock divider bit position for UART1 */ +#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8)) +/** Peripheral clock divider bit position for PWM1 */ +#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12)) +/** Peripheral clock divider bit position for I2C0 */ +#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14)) +/** Peripheral clock divider bit position for SPI */ +#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16)) +/** Peripheral clock divider bit position for SSP1 */ +#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20)) +/** Peripheral clock divider bit position for DAC */ +#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22)) +/** Peripheral clock divider bit position for ADC */ +#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24)) +/** Peripheral clock divider bit position for CAN1 */ +#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26)) +/** Peripheral clock divider bit position for CAN2 */ +#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28)) +/** Peripheral clock divider bit position for ACF */ +#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30)) +/** Peripheral clock divider bit position for QEI */ +#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32)) +/** Peripheral clock divider bit position for PCB */ +#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36)) +/** Peripheral clock divider bit position for I2C1 */ +#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38)) +/** Peripheral clock divider bit position for SSP0 */ +#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42)) +/** Peripheral clock divider bit position for TIMER2 */ +#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44)) +/** Peripheral clock divider bit position for TIMER3 */ +#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46)) +/** Peripheral clock divider bit position for UART2 */ +#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48)) +/** Peripheral clock divider bit position for UART3 */ +#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50)) +/** Peripheral clock divider bit position for I2C2 */ +#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52)) +/** Peripheral clock divider bit position for I2S */ +#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54)) +/** Peripheral clock divider bit position for RIT */ +#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58)) +/** Peripheral clock divider bit position for SYSCON */ +#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60)) +/** Peripheral clock divider bit position for MC */ +#define CLKPWR_PCLKSEL_MC ((uint32_t)(62)) + +/** Macro for Peripheral Clock Selection register bit values + * Note: When CCLK_DIV_8, Peripheral’s clock is selected to + * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering + * when ’11’selects PCLK_xyz = CCLK/6 */ +/* Peripheral clock divider is set to 4 from CCLK */ +#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0)) +/** Peripheral clock divider is the same with CCLK */ +#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1)) +/** Peripheral clock divider is set to 2 from CCLK */ +#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2)) + + +/******************************************************************** +* Power Control for Peripherals Definitions +**********************************************************************/ +/** Timer/Counter 0 power/clock control bit */ +#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) +/* Timer/Counter 1 power/clock control bit */ +#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) +/** UART0 power/clock control bit */ +#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) +/** UART1 power/clock control bit */ +#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) +/** PWM1 power/clock control bit */ +#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) +/** The I2C0 interface power/clock control bit */ +#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) +/** The SPI interface power/clock control bit */ +#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8)) +/** The RTC power/clock control bit */ +#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) +/** The SSP1 interface power/clock control bit */ +#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) +/** A/D converter 0 (ADC0) power/clock control bit */ +#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12)) +/** CAN Controller 1 power/clock control bit */ +#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) +/** CAN Controller 2 power/clock control bit */ +#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) +/** GPIO power/clock control bit */ +#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) +/** Repetitive Interrupt Timer power/clock control bit */ +#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16)) +/** Motor Control PWM */ +#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17)) +/** Quadrature Encoder Interface power/clock control bit */ +#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) +/** The I2C1 interface power/clock control bit */ +#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) +/** The SSP0 interface power/clock control bit */ +#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) +/** Timer 2 power/clock control bit */ +#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) +/** Timer 3 power/clock control bit */ +#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) +/** UART 2 power/clock control bit */ +#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) +/** UART 3 power/clock control bit */ +#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) +/** I2C interface 2 power/clock control bit */ +#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) +/** I2S interface power/clock control bit*/ +#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) +/** GP DMA function power/clock control bit*/ +#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) +/** Ethernet block power/clock control bit*/ +#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) +/** USB interface power/clock control bit*/ +#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) + + +/** + * @} + */ +/* Private Macros ------------------------------------------------------------- */ +/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros + * @{ + */ + +/* --------------------- BIT DEFINITIONS -------------------------------------- */ +/*********************************************************************//** + * Macro defines for Clock Source Select Register + **********************************************************************/ +/** Internal RC oscillator */ +#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00)) +/** Main oscillator */ +#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01)) +/** RTC oscillator */ +#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02)) +/** Clock source selection bit mask */ +#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03)) + +/*********************************************************************//** + * Macro defines for Clock Output Configuration Register + **********************************************************************/ +/* Clock Output Configuration register definition */ +/** Selects the CPU clock as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00)) +/** Selects the main oscillator as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01)) +/** Selects the Internal RC oscillator as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02)) +/** Selects the USB clock as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03)) +/** Selects the RTC oscillator as the CLKOUT source */ +#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04)) +/** Integer value to divide the output clock by, minus one */ +#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4)) +/** CLKOUT enable control */ +#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8)) +/** CLKOUT activity indication */ +#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9)) +/** Clock source selection bit mask */ +#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF)) + +/*********************************************************************//** + * Macro defines for PPL0 Control Register + **********************************************************************/ +/** PLL 0 control enable */ +#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01)) +/** PLL 0 control connect */ +#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02)) +/** PLL 0 control bit mask */ +#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03)) + +/*********************************************************************//** + * Macro defines for PPL0 Configuration Register + **********************************************************************/ +/** PLL 0 Configuration MSEL field */ +#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF)) +/** PLL 0 Configuration NSEL field */ +#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000)) +/** PLL 0 Configuration bit mask */ +#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF)) + + +/*********************************************************************//** + * Macro defines for PPL0 Status Register + **********************************************************************/ +/** PLL 0 MSEL value */ +#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF)) +/** PLL NSEL get value */ +#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF)) +/** PLL status enable bit */ +#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24)) +/** PLL status Connect bit */ +#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25)) +/** PLL status lock */ +#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26)) + +/*********************************************************************//** + * Macro defines for PPL0 Feed Register + **********************************************************************/ +/** PLL0 Feed bit mask */ +#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF) + +/*********************************************************************//** + * Macro defines for PLL1 Control Register + **********************************************************************/ +/** USB PLL control enable */ +#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01)) +/** USB PLL control connect */ +#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02)) +/** USB PLL control bit mask */ +#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03)) + +/*********************************************************************//** + * Macro defines for PLL1 Configuration Register + **********************************************************************/ +/** USB PLL MSEL set value */ +#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F)) +/** USB PLL PSEL set value */ +#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5)) +/** USB PLL configuration bit mask */ +#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F)) + +/*********************************************************************//** + * Macro defines for PLL1 Status Register + **********************************************************************/ +/** USB PLL MSEL get value */ +#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F)) +/** USB PLL PSEL get value */ +#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03)) +/** USB PLL status enable bit */ +#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8)) +/** USB PLL status Connect bit */ +#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9)) +/** USB PLL status lock */ +#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10)) + +/*********************************************************************//** + * Macro defines for PLL1 Feed Register + **********************************************************************/ +/** PLL1 Feed bit mask */ +#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF) + +/*********************************************************************//** + * Macro defines for CPU Clock Configuration Register + **********************************************************************/ +/** CPU Clock configuration bit mask */ +#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF)) + +/*********************************************************************//** + * Macro defines for USB Clock Configuration Register + **********************************************************************/ +/** USB Clock Configuration bit mask */ +#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F)) + +/*********************************************************************//** + * Macro defines for IRC Trim Register + **********************************************************************/ +/** IRC Trim bit mask */ +#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F)) + +/*********************************************************************//** + * Macro defines for Peripheral Clock Selection Register 0 and 1 + **********************************************************************/ +/** Peripheral Clock Selection 0 mask bit */ +#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF)) +/** Peripheral Clock Selection 1 mask bit */ +#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3)) +/** Macro to set peripheral clock of each type + * p: position of two bits that hold divider of peripheral clock + * n: value of divider of peripheral clock to be set */ +#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n) +/** Macro to mask peripheral clock of each type */ +#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03) +/** Macro to get peripheral clock of each type */ +#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03)) + +/*********************************************************************//** + * Macro defines for Power Mode Control Register + **********************************************************************/ +/** Power mode control bit 0 */ +#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0)) +/** Power mode control bit 1 */ +#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1)) +/** Brown-Out Reduced Power Mode */ +#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2)) +/** Brown-Out Global Disable */ +#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3)) +/** Brown Out Reset Disable */ +#define CLKPWR_PCON_BORD ((uint32_t)(1<<4)) +/** Sleep Mode entry flag */ +#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8)) +/** Deep Sleep entry flag */ +#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9)) +/** Power-down entry flag */ +#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10)) +/** Deep Power-down entry flag */ +#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11)) + +/*********************************************************************//** + * Macro defines for Power Control for Peripheral Register + **********************************************************************/ +/** Power Control for Peripherals bit mask */ +#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE + +/** + * @} + */ + + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions + * @{ + */ + +void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal); +uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType); +uint32_t CLKPWR_GetPCLK (uint32_t ClkType); +void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState); +void CLKPWR_Sleep(void); +void CLKPWR_DeepSleep(void); +void CLKPWR_PowerDown(void); +void CLKPWR_DeepPowerDown(void); + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LPC17XX_CLKPWR_H_ */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */ diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_dac.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_dac.h new file mode 100644 index 0000000..1e382b7 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_dac.h @@ -0,0 +1,142 @@ +/***********************************************************************//** + * @file lpc17xx_dac.h + * @brief Contains all macro definitions and function prototypes + * support for DAC firmware library on LPC17xx + * @version 3.0 + * @date 18. June. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup DAC DAC + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_DAC_H_ +#define LPC17XX_DAC_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "LPC17xx.h" +#include "lpc_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public Macros -------------------------------------------------------------- */ +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ + +/** After the selected settling time after this field is written with a +new VALUE, the voltage on the AOUT pin (with respect to VSSA) +is VALUE/1024 × VREF */ +#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6)) +/** If this bit = 0: The settling time of the DAC is 1 microsecond max, + * and the maximum current is 700 microAmpere + * If this bit = 1: The settling time of the DAC is 2.5 microsecond + * and the maximum current is 350 microAmpere */ +#define DAC_BIAS_EN ((uint32_t)(1<<16)) +/** Value to reload interrupt DMA counter */ +#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff)) + +/** DCAR double buffering */ +#define DAC_DBLBUF_ENA ((uint32_t)(1<<1)) +/** DCAR Time out count enable */ +#define DAC_CNT_ENA ((uint32_t)(1<<2)) +/** DCAR DMA access */ +#define DAC_DMA_ENA ((uint32_t)(1<<3)) +/** DCAR DACCTRL mask bit */ +#define DAC_DACCTRL_MASK ((uint32_t)(0x0F)) + +/** Macro to determine if it is valid DAC peripheral */ +#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC)) + +/** Macro to check DAC current optional parameter */ +#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\ +||(OPTION == DAC_MAX_CURRENT_350uA)) +/** + * @} + */ +/* Public Types --------------------------------------------------------------- */ +/** @defgroup DAC_Public_Types DAC Public Types + * @{ + */ + +/** + * @brief Current option in DAC configuration option */ +typedef enum +{ + DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max, + and the maximum current is 700 uA */ + DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us + and the maximum current is 350 uA */ +} DAC_CURRENT_OPT; + +/** + * @brief Configuration for DAC converter control register */ +typedef struct +{ + + uint8_t DBLBUF_ENA; /**< + -0: Disable DACR double buffering + -1: when bit CNT_ENA, enable DACR double buffering feature + */ + uint8_t CNT_ENA; /*!< + -0: Time out counter is disable + -1: Time out conter is enable + */ + uint8_t DMA_ENA; /*!< + -0: DMA access is disable + -1: DMA burst request + */ + uint8_t RESERVED; + +} DAC_CONVERTER_CFG_Type; + +/** + * @} + */ + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup DAC_Public_Functions DAC Public Functions + * @{ + */ + +void DAC_Init(LPC_DAC_TypeDef *DACx); +void DAC_UpdateValue (LPC_DAC_TypeDef *DACx, uint32_t dac_value); +void DAC_SetBias (LPC_DAC_TypeDef *DACx,uint32_t bias); +void DAC_ConfigDAConverterControl (LPC_DAC_TypeDef *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct); +void DAC_SetDMATimeOut(LPC_DAC_TypeDef *DACx,uint32_t time_out); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* LPC17XX_DAC_H_ */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */ + diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_emac.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_emac.h new file mode 100644 index 0000000..5055049 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_emac.h @@ -0,0 +1,699 @@ +/***********************************************************************//** + * @file lpc17xx_emac.h + * @brief Contains all macro definitions and function prototypes + * support for Ethernet MAC firmware library on LPC17xx + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup EMAC EMAC + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_EMAC_H_ +#define LPC17XX_EMAC_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "LPC17xx.h" +#include "lpc_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define MCB_LPC_1768 +//#define IAR_LPC_1768 + +/* Public Macros -------------------------------------------------------------- */ +/** @defgroup EMAC_Public_Macros EMAC Public Macros + * @{ + */ + + +/* EMAC PHY status type definitions */ +#define EMAC_PHY_STAT_LINK (0) /**< Link Status */ +#define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */ +#define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */ + +/* EMAC PHY device Speed definitions */ +#define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */ +#define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */ +#define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */ +#define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */ +#define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */ + +/** + * @} + */ +/* Private Macros ------------------------------------------------------------- */ +/** @defgroup EMAC_Private_Macros EMAC Private Macros + * @{ + */ + + +/* EMAC Memory Buffer configuration for 16K Ethernet RAM */ +#define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */ +#define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */ +#define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */ +#define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */ + +/* --------------------- BIT DEFINITIONS -------------------------------------- */ +/*********************************************************************//** + * Macro defines for MAC Configuration Register 1 + **********************************************************************/ +#define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */ +#define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */ +#define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */ +#define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */ +#define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */ +#define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */ +#define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */ +#define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */ +#define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */ +#define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */ +#define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */ + +/*********************************************************************//** + * Macro defines for MAC Configuration Register 2 + **********************************************************************/ +#define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */ +#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */ +#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */ +#define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */ +#define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */ +#define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */ +#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */ +#define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */ +#define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */ +#define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */ +#define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */ +#define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */ +#define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */ + +/*********************************************************************//** + * Macro defines for Back-to-Back Inter-Packet-Gap Register + **********************************************************************/ +/** Programmable field representing the nibble time offset of the minimum possible period + * between the end of any transmitted packet to the beginning of the next */ +#define EMAC_IPGT_BBIPG(n) (n&0x7F) +/** Recommended value for Full Duplex of Programmable field representing the nibble time + * offset of the minimum possible period between the end of any transmitted packet to the + * beginning of the next */ +#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15)) +/** Recommended value for Half Duplex of Programmable field representing the nibble time + * offset of the minimum possible period between the end of any transmitted packet to the + * beginning of the next */ +#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12)) + +/*********************************************************************//** + * Macro defines for Non Back-to-Back Inter-Packet-Gap Register + **********************************************************************/ +/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */ +#define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F) +/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */ +#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12)) +/** Programmable field representing the optional carrierSense window referenced in + * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */ +#define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8) +/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */ +#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C) + +/*********************************************************************//** + * Macro defines for Collision Window/Retry Register + **********************************************************************/ +/** Programmable field specifying the number of retransmission attempts following a collision before + * aborting the packet due to excessive collisions */ +#define EMAC_CLRT_MAX_RETX(n) (n&0x0F) +/** Programmable field representing the slot time or collision window during which collisions occur + * in properly configured networks */ +#define EMAC_CLRT_COLL(n) ((n&0x3F)<<8) +/** Default value for Collision Window / Retry register */ +#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37))) + +/*********************************************************************//** + * Macro defines for Maximum Frame Register + **********************************************************************/ +/** Represents a maximum receive frame of 1536 octets */ +#define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF) + +/*********************************************************************//** + * Macro defines for PHY Support Register + **********************************************************************/ +#define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */ +#define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */ + +/*********************************************************************//** + * Macro defines for Test Register + **********************************************************************/ +#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */ +#define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */ +#define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */ + +/*********************************************************************//** + * Macro defines for MII Management Configuration Register + **********************************************************************/ +#define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */ +#define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */ +#define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */ +#define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */ +#define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */ + +/*********************************************************************//** + * Macro defines for MII Management Command Register + **********************************************************************/ +#define EMAC_MCMD_READ 0x00000001 /**< MII Read */ +#define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */ + +#define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */ +#define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */ + +/*********************************************************************//** + * Macro defines for MII Management Address Register + **********************************************************************/ +#define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */ +#define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */ + +/*********************************************************************//** + * Macro defines for MII Management Write Data Register + **********************************************************************/ +#define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */ + +/*********************************************************************//** + * Macro defines for MII Management Read Data Register + **********************************************************************/ +#define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */ + +/*********************************************************************//** + * Macro defines for MII Management Indicators Register + **********************************************************************/ +#define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */ +#define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */ +#define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */ +#define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */ + +/* Station Address 0 Register */ +/* Station Address 1 Register */ +/* Station Address 2 Register */ + + +/* Control register definitions --------------------------------------------------------------------------- */ +/*********************************************************************//** + * Macro defines for Command Register + **********************************************************************/ +#define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */ +#define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */ +#define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */ +#define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */ +#define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */ +#define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */ +#define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */ +#define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */ +#define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */ +#define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */ + +/*********************************************************************//** + * Macro defines for Status Register + **********************************************************************/ +#define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */ +#define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */ + +/*********************************************************************//** + * Macro defines for Transmit Status Vector 0 Register + **********************************************************************/ +#define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */ +#define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */ +#define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */ +#define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */ +#define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */ +#define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */ +#define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */ +#define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */ +#define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */ +#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */ +#define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */ +#define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */ +#define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */ +#define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */ +#define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */ +#define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */ +#define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */ + +/*********************************************************************//** + * Macro defines for Transmit Status Vector 1 Register + **********************************************************************/ +#define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */ +#define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */ + +/*********************************************************************//** + * Macro defines for Receive Status Vector Register + **********************************************************************/ +#define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */ +#define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */ +#define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */ +#define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */ +#define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */ +#define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */ +#define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */ +#define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */ +#define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */ +#define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */ +#define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */ +#define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */ +#define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */ +#define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */ +#define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */ +#define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */ + +/*********************************************************************//** + * Macro defines for Flow Control Counter Register + **********************************************************************/ +#define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */ +#define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */ + +/*********************************************************************//** + * Macro defines for Flow Control Status Register + **********************************************************************/ +#define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */ + + +/* Receive filter register definitions -------------------------------------------------------- */ +/*********************************************************************//** + * Macro defines for Receive Filter Control Register + **********************************************************************/ +#define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */ +#define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */ +#define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */ +#define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */ +#define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/ +#define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */ +#define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */ +#define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */ + +/*********************************************************************//** + * Macro defines for Receive Filter WoL Status/Clear Registers + **********************************************************************/ +#define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */ +#define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */ +#define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */ +#define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */ +#define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */ +#define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */ +#define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */ +#define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */ +#define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */ + + +/* Module control register definitions ---------------------------------------------------- */ +/*********************************************************************//** + * Macro defines for Interrupt Status/Enable/Clear/Set Registers + **********************************************************************/ +#define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */ +#define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */ +#define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */ +#define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */ +#define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */ +#define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */ +#define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */ +#define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */ +#define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */ +#define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */ + +/*********************************************************************//** + * Macro defines for Power Down Register + **********************************************************************/ +#define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */ + +/* Descriptor and status formats ---------------------------------------------------- */ +/*********************************************************************//** + * Macro defines for RX Descriptor Control Word + **********************************************************************/ +#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */ +#define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */ + +/*********************************************************************//** + * Macro defines for RX Status Hash CRC Word + **********************************************************************/ +#define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */ +#define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */ + +/*********************************************************************//** + * Macro defines for RX Status Information Word + **********************************************************************/ +#define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */ +#define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */ +#define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */ +#define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */ +#define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */ +#define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */ +#define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */ +#define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */ +#define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */ +#define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */ +#define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */ +#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */ +#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */ +#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */ +#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ +#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \ +EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) + +/*********************************************************************//** + * Macro defines for TX Descriptor Control Word + **********************************************************************/ +#define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */ +#define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */ +#define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */ +#define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */ +#define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */ +#define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */ +#define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */ + +/*********************************************************************//** + * Macro defines for TX Status Information Word + **********************************************************************/ +#define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */ +#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */ +#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */ +#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */ +#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */ +#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */ +#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */ +#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ + +#ifdef MCB_LPC_1768 +/* DP83848C PHY definition ------------------------------------------------------------ */ + +/** PHY device reset time out definition */ +#define EMAC_PHY_RESP_TOUT 0x100000UL + +/* ENET Device Revision ID */ +#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */ + +/*********************************************************************//** + * Macro defines for DP83848C PHY Registers + **********************************************************************/ +#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */ +#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */ +#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ +#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ +#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ +#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ +#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ +#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ +#define EMAC_PHY_REG_LPNPA 0x08 + +/*********************************************************************//** + * Macro defines for PHY Extended Registers + **********************************************************************/ +#define EMAC_PHY_REG_STS 0x10 /**< Status Register */ +#define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */ +#define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */ +#define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */ +#define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */ +#define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */ +#define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */ +#define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */ +#define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */ +#define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */ +#define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */ +#define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */ + +/*********************************************************************//** + * Macro defines for PHY Basic Mode Control Register + **********************************************************************/ +#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */ +#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */ +#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */ +#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */ +#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */ +#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */ +#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */ +#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */ + +/*********************************************************************//** + * Macro defines for PHY Basic Mode Status Status Register + **********************************************************************/ +#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */ +#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */ +#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */ +#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */ +#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */ +#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */ +#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */ +#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */ +#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */ +#define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */ + +/*********************************************************************//** + * Macro defines for PHY Status Register + **********************************************************************/ +#define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */ +#define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */ +#define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */ +#define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */ +#define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */ +#define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */ +#define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */ + +#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */ +#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */ +#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */ +#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */ +#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */ + +#define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */ +#define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */ + +#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13)) +#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12)) +#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */ + +#elif defined(IAR_LPC_1768) +/* KSZ8721BL PHY definition ------------------------------------------------------------ */ +/** PHY device reset time out definition */ +#define EMAC_PHY_RESP_TOUT 0x100000UL + +/* ENET Device Revision ID */ +#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */ + +/*********************************************************************//** + * Macro defines for KSZ8721BL PHY Registers + **********************************************************************/ +#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */ +#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */ +#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ +#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ +#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ +#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ +#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ +#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ +#define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */ +#define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */ +#define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */ +#define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */ + +/*********************************************************************//** + * Macro defines for PHY Basic Mode Control Register + **********************************************************************/ +#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */ +#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */ +#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */ +#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */ +#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */ +#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */ +#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */ +#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */ +#define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */ +#define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */ + +/*********************************************************************//** + * Macro defines for PHY Basic Mode Status Register + **********************************************************************/ +#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */ +#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */ +#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */ +#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */ +#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */ +#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */ +#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */ +#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */ +#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */ +#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */ +#define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */ +#define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */ + +/*********************************************************************//** + * Macro defines for PHY Identifier + **********************************************************************/ +/* PHY Identifier 1 bitmap definitions */ +#define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */ + +/* PHY Identifier 2 bitmap definitions */ +#define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */ + +/*********************************************************************//** + * Macro defines for Auto-Negotiation Advertisement + **********************************************************************/ +#define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */ +#define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */ +#define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */ +#define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */ +#define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */ +#define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */ +#define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */ +#define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */ +#define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */ + +#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */ +#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */ +#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */ +#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */ +#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */ + +#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13)) +#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12)) + +#define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */ +#define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */ +#endif + +/** + * @} + */ + + +/* Public Types --------------------------------------------------------------- */ +/** @defgroup EMAC_Public_Types EMAC Public Types + * @{ + */ + +/* Descriptor and status formats ---------------------------------------------- */ + +/** + * @brief RX Descriptor structure type definition + */ +typedef struct { + uint32_t Packet; /**< Receive Packet Descriptor */ + uint32_t Ctrl; /**< Receive Control Descriptor */ +} RX_Desc; + +/** + * @brief RX Status structure type definition + */ +typedef struct { + uint32_t Info; /**< Receive Information Status */ + uint32_t HashCRC; /**< Receive Hash CRC Status */ +} RX_Stat; + +/** + * @brief TX Descriptor structure type definition + */ +typedef struct { + uint32_t Packet; /**< Transmit Packet Descriptor */ + uint32_t Ctrl; /**< Transmit Control Descriptor */ +} TX_Desc; + +/** + * @brief TX Status structure type definition + */ +typedef struct { + uint32_t Info; /**< Transmit Information Status */ +} TX_Stat; + + +/** + * @brief TX Data Buffer structure definition + */ +typedef struct { + uint32_t ulDataLen; /**< Data length */ + uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */ +} EMAC_PACKETBUF_Type; + +/** + * @brief EMAC configuration structure definition + */ +typedef struct { + uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following: + - EMAC_MODE_AUTO + - EMAC_MODE_10M_FULL + - EMAC_MODE_10M_HALF + - EMAC_MODE_100M_FULL + - EMAC_MODE_100M_HALF + */ + uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes + of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5]) + */ +} EMAC_CFG_Type; + + +/** + * @} + */ + + +/* Public Functions ----------------------------------------------------------- */ +/** @defgroup EMAC_Public_Functions EMAC Public Functions + * @{ + */ +/* Init/DeInit EMAC peripheral */ +Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct); +void EMAC_DeInit(void); + +/* PHY functions --------------*/ +int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState); +int32_t EMAC_SetPHYMode(uint32_t ulPHYMode); +int32_t EMAC_UpdatePHYStatus(void); + +/* Filter functions ----------*/ +void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState); +void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState); + +/* EMAC Packet Buffer functions */ +void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct); +void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct); + +/* EMAC Interrupt functions -------*/ +void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState); +IntStatus EMAC_IntGetStatus(uint32_t ulIntType); + +/* EMAC Index functions -----------*/ +Bool EMAC_CheckReceiveIndex(void); +Bool EMAC_CheckTransmitIndex(void); +void EMAC_UpdateRxConsumeIndex(void); +void EMAC_UpdateTxProduceIndex(void); + +FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType); +uint32_t EMAC_GetReceiveDataSize(void); +FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* LPC17XX_EMAC_H_ */ + +/** + * @} + */ + +/* --------------------------------- End Of File ------------------------------ */ diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_exti.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_exti.h new file mode 100644 index 0000000..91ebb87 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_exti.h @@ -0,0 +1,143 @@ +/***********************************************************************//** + * @file lpc17xx_exti.h + * @brief Contains all macro definitions and function prototypes + * support for External interrupt firmware library on LPC17xx + * @version 2.0 + * @date 21. May. 2010 + * @author NXP MCU SW Application Team + ************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + **************************************************************************/ + +/* Peripheral group ----------------------------------------------------------- */ +/** @defgroup EXTI EXTI + * @ingroup LPC1700CMSIS_FwLib_Drivers + * @{ + */ + +#ifndef LPC17XX_EXTI_H_ +#define LPC17XX_EXTI_H_ + +/* Includes ------------------------------------------------------------------- */ +#include "LPC17xx.h" +#include "lpc_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/* Private Macros ------------------------------------------------------------- */ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +/*********************************************************************//** + * Macro defines for EXTI control register + **********************************************************************/ +#define EXTI_EINT0_BIT_MARK 0x01 +#define EXTI_EINT1_BIT_MARK 0x02 +#define EXTI_EINT2_BIT_MARK 0x04 +#define EXTI_EINT3_BIT_MARK 0x08 + +/** + * @} + */ + +/* Private Macros ------------------------------------------------------------- */ +/** @defgroup EXTI_Public_Types EXTI Public Types + * @{ + */ + +/** + * @brief EXTI external interrupt line option + */ +typedef enum +{ + EXTI_EINT0, /*!< External interrupt 0, P2.10 */ + EXTI_EINT1, /*!< External interrupt 0, P2.11 */ + EXTI_EINT2, /*!< External interrupt 0, P2.12 */ + EXTI_EINT3 /*!< External interrupt 0, P2.13 */ +} EXTI_LINE_ENUM; + +/** + * @brief EXTI mode option + */ +typedef enum +{ + EXTI_MODE_LEVEL_SENSITIVE, /*!< Level sensitivity is selected */ + EXTI_MODE_EDGE_SENSITIVE /*!< Edge sensitivity is selected */ +} EXTI_MODE_ENUM; + +/** + * @brief EXTI polarity option + */ +typedef enum +{ + EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE, /*!< Low active or falling edge sensitive + depending on pin mode */ + EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE /*!< High active or rising edge sensitive + depending on pin mode */ +} EXTI_POLARITY_ENUM; + +/** + * @brief EXTI Initialize structure + */ +typedef struct +{ + EXTI_LINE_ENUM EXTI_Line; /*!