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authorPixel <>2001-04-16 22:47:34 +0000
committerPixel <>2001-04-16 22:47:34 +0000
commitb77b22b3bd99c03b032cbd47465b1cbe34821120 (patch)
tree7ae93778e189d7f67ee9f72fb3a813883558647a /lib/simulator.c
parentcb850755d0ca7c625fe418ef6b9770876c3308f2 (diff)
Blouarf
Diffstat (limited to 'lib/simulator.c')
-rw-r--r--lib/simulator.c26
1 files changed, 20 insertions, 6 deletions
diff --git a/lib/simulator.c b/lib/simulator.c
index 9a859f4..802587b 100644
--- a/lib/simulator.c
+++ b/lib/simulator.c
@@ -98,8 +98,10 @@ void DecodeExec(Uint32 instruction)
Uint32 champ_registre_resultat, val1, val2, resultat;
int test1, test2;
Uint32 val; /* valeur qui va etre stockée */
-
+
+
if (Opcode(instruction) & 0x80) {
+ fprintf(stderr, "Opcode FPU\n");
fpu(Opcode(instruction));
} else {
switch (Opcode(instruction)) {
@@ -111,6 +113,7 @@ void DecodeExec(Uint32 instruction)
case 5:
case 6:
case 7:
+ fprintf(stderr, "Opcode ALU\n");
/* ALU */
champ_registre_resultat = Champ1(instruction); /* Champ du registre dans lequel va etre stocké le résultat */
val1 = LireRegistre(Champ2(instruction)); /* Premier entier qui va etre utilisé dans l'opération */
@@ -185,6 +188,7 @@ void DecodeExec(Uint32 instruction)
}
break;
case 8: /* MOV */
+ fprintf(stderr, "Opcode MOV\n");
if (ValeurBit(Extension(instruction), 4) == 1) { /* MOV conditionnel */
if (ValeurBit(Extension(instruction), 5) == 0) { /* Test normal */
switch (champ(Extension(instruction) >> 2, 4)) { /* teste les bits 2 et 3 */
@@ -220,28 +224,38 @@ void DecodeExec(Uint32 instruction)
}
/* Pas de MOV conditionnel */
if (ValeurBit(Extension(instruction), 1) == 0) { /* Mov arg1 arg2 */
+ fprintf(stderr, "MOV arg1, arg2\n");
if (ValeurBit(Extension(instruction), 0) == 0) { /* arg2 = reg */
+ fprintf(stderr, "arg2 = reg (%i)\n", Champ2(instruction));
if (champ(Champ1(instruction), 2) == 0) { /* r/m de arg1 = 0 */
+ fprintf(stderr, "arg1 = reg (%i)\n", Champ3(instruction));
EcrireRegistre(Champ3(instruction), LireRegistre(Champ2(instruction)));
} else {
+ fprintf(stderr, "arg1 = adresse\n");
ST(Adresse(Champ1(instruction), instruction),
LireRegistre(Champ2(instruction)));
}
} else { /* arg2 = imm32 */
+ fprintf(stderr, "arg2 = imm (%i)\n", LireInstruction());
if (champ(Champ1(instruction), 2) == 0) { /* r/m de arg1 = 0 */
+ fprintf(stderr, "arg1 = reg (%i)\n", Champ3(instruction));
EcrireRegistre(Champ3(instruction), LireInstruction());
IncrementeCompteurOrdinal();
} else {
+ fprintf(stderr, "arg1 = adresse\n");
ST(Adresse(Champ1(instruction), instruction), LireInstruction());
IncrementeCompteurOrdinal();
}
}
} else {
+ fprintf(stderr, "MOV arg2, arg1\n");
if (ValeurBit(Extension(instruction), 0) == 0) { /* arg2 = reg */
+ fprintf(stderr, "arg2 = reg (%i)\n", Champ2(instruction));
if (champ(Champ1(instruction), 2) == 0) { /* r/m de arg1 = 0 */
+ fprintf(stderr, "arg1 = reg (%i)\n", Champ3(instruction));
EcrireRegistre(Champ2(instruction), LireRegistre(Champ3(instruction)));
-
} else {
+ fprintf(stderr, "arg1 = addresse\n");
EcrireRegistre(Champ2(instruction),
LD(Adresse(Champ1(instruction), instruction)));
}
@@ -392,10 +406,13 @@ void AfficheReg(void) // affiche reg
void Debogueur(void)
{
int out = 0;
+
+ Uint32 instruction = LireInstruction();
while (!out) {
AfficheReg();
- fprintf(stderr, "%08lX:%08lX > ", LireRegistrePC(), LD(LireRegistrePC()));
+ fprintf(stderr, "Opcode: %02X, extension: %02X, champ1: %02X, champ2: %02X, champ3: %02X\n", Opcode(instruction), Extension(instruction), Champ1(instruction), Champ2(instruction), Champ3(instruction));
+ fprintf(stderr, "%08lX:%08lX > ", LireRegistrePC(), instruction);
switch (fgetc(input)) {
case 'G':
@@ -438,11 +455,8 @@ void Traitement(Uint32 entrypoint)
Debogueur();
clearterm();
}
- fprintf(stderr, "Kapoue1\n");
instruction = LireInstruction();
- fprintf(stderr, "Kapoue2\n");
IncrementeCompteurOrdinal();
- fprintf(stderr, "Kapoue3\n");
DecodeExec(instruction);
}
}