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-rwxr-xr-xbuild.sh11
-rw-r--r--piodev1.prj1
-rw-r--r--piodev1.ucf61
-rw-r--r--piodev1.v93
-rw-r--r--piodev1.xst29
5 files changed, 195 insertions, 0 deletions
diff --git a/build.sh b/build.sh
new file mode 100755
index 0000000..e9668f6
--- /dev/null
+++ b/build.sh
@@ -0,0 +1,11 @@
+#!/bin/bash
+set -xe
+
+. /opt/Xilinx/14.7/ISE_DS/settings64.sh
+mkdir -p xst/projnav.tmp
+xst -intstyle ise -ifn piodev1.xst -ofn piodev1.syr
+ngdbuild -intstyle ise -dd _ngo -uc piodev1.ucf -p xc9572xl-VQ64-5 piodev1.ngc piodev1.ngd
+cpldfit -intstyle ise -p xc9572xl-5-VQ64 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper piodev1.ngd
+XSLTProcess piodev1_build.xml
+tsim -intstyle ise piodev1 piodev1.nga
+hprep6 -s IEEE1149 -n piodev1 -i piodev1
diff --git a/piodev1.prj b/piodev1.prj
new file mode 100644
index 0000000..df6d963
--- /dev/null
+++ b/piodev1.prj
@@ -0,0 +1 @@
+verilog work "piodev1.v"
diff --git a/piodev1.ucf b/piodev1.ucf
new file mode 100644
index 0000000..f0dc682
--- /dev/null
+++ b/piodev1.ucf
@@ -0,0 +1,61 @@
+NET nIN_CH LOC=P1;
+NET nCS_CH LOC=P2;
+
+NET D<7> LOC=P4;
+NET D<6> LOC=P5;
+NET D<5> LOC=P6;
+NET D<4> LOC=P7;
+NET D<3> LOC=P8;
+NET D<2> LOC=P9;
+NET D<1> LOC=P10;
+NET D<0> LOC=P11;
+
+NET A20_SRAM LOC=P12;
+NET nCS_SRAM LOC=P13;
+
+NET nRD LOC=P15;
+NET nRD BUFG=CLK;
+NET nWR LOC=P16;
+NET nWR BUFG=CLK;
+
+NET CLK LOC=P17;
+NET CLK BUFG=CLK;
+
+NET nCS_SW LOC=P18;
+NET WR_LEDS LOC=P19;
+
+NET SWRESET LOC=P23 PULLUP;
+NET RECOVERY LOC=P28 PULLUP;
+
+NET nIN10 LOC=P31;
+NET nCS0 LOC=P32;
+NET nCS2 LOC=P33;
+NET SBEN LOC=P34;
+
+NET PD<1> LOC=P35;
+NET PD<0> LOC=P36;
+NET PD<3> LOC=P38;
+NET PD<2> LOC=P39;
+NET PD<5> LOC=P40;
+NET PD<4> LOC=P42;
+NET PD<7> LOC=P43;
+NET PD<6> LOC=P44;
+
+NET A0 LOC=P45;
+NET A1 LOC=P46;
+NET A2 LOC=P47;
+NET A3 LOC=P48;
+NET A20 LOC=P49;
+NET A21 LOC=P50;
+NET A22 LOC=P51;
+
+NET A20_FLASH LOC=P52;
+NET nCS_FLASH LOC=P56;
+
+NET nCS_PORTA LOC=P58;
+NET nCS_PORTB LOC=P59;
+NET A0_PORTA LOC=P60;
+NET nRST_FT LOC=P61;
+
+NET nRST LOC=P64;
+NET nRST BUFG=SR;
diff --git a/piodev1.v b/piodev1.v
new file mode 100644
index 0000000..4f84636
--- /dev/null
+++ b/piodev1.v
@@ -0,0 +1,93 @@
+module piodev1(
+ input nIN_CH,
+ output nCS_CH,
+
+ inout [0:7] D,
+
+ output A20_SRAM,
+ output nCS_SRAM,
+
+ input nRD,
+ input nWR,
+
+ input CLK,
+
+ output nCS_SW,
+ output WR_LEDS,
+
+ input SWRESET,
+ input RECOVERY,
+
+ output nIN10,
+ input nCS0,
+ input nCS2,
+ output SBEN,
+
+ inout [0:7] PD,
+
+ input A0,
+ input A1,
+ input A2,
+ input A3,
+ input A20,
+ input A21,
+ input A22,
+
+ output A20_FLASH,
+ output nCS_FLASH,
+
+ output nCS_PORTA,
+ output nCS_PORTB,
+ output A0_PORTA,
+ output nRST_FT,
+
+ input NRST
+ );
+
+wire CS0 = !nCS0;
+wire CS2 = !nCS2;
+
+wire CS_FLASH = CS2;
+wire CS_PORTA = CS0;
+
+assign nCS_FLASH = !CS_FLASH;
+assign nCS_PORTA = !CS_PORTA;
+
+assign SBEN = 1'b1;
+
+assign A20_FLASH = A20;
+
+assign A0_PORTA = 1'b0;
+
+assign nCS_PORTB = 1'b1;
+assign nRST_FT = 1'b1;
+
+reg PDtoD = 1'b0;
+reg [7:0] buffer = 0;
+
+wire activateOutput = CS0 | CS2;
+
+always @(negedge nWR or negedge nRD) begin
+ if (!nWR) begin
+ PDtoD <= 1'b0;
+ end
+
+ if (!nRD) begin
+ PDtoD <= 1'b1;
+ end
+end
+
+always @(posedge nWR or posedge nRD) begin
+ if (nWR) begin
+ buffer <= D;
+ end
+
+ if (nRD) begin
+ buffer <= PD;
+ end
+end
+
+assign D = (PDtoD && activateOutput) ? buffer : 8'bzzzzzzzz;
+assign PD = !PDtoD ? buffer : 8'bzzzzzzzz;
+
+endmodule
diff --git a/piodev1.xst b/piodev1.xst
new file mode 100644
index 0000000..cb30796
--- /dev/null
+++ b/piodev1.xst
@@ -0,0 +1,29 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn piodev1.prj
+-ifmt mixed
+-ofn piodev1
+-ofmt NGC
+-p xc9500xl
+-top piodev1
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy Yes
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-mux_extract Yes
+-resource_sharing YES
+-iobuf YES
+-pld_mp YES
+-pld_xp YES
+-pld_ce YES
+-wysiwyg NO
+-equivalent_register_removal YES