Shuffling a few files around, and adding assembly file support.

2 files changed, 453 insertions, 0 deletions

diff --git a/arch/arm/lpc17xx/ldscript b/arch/arm/lpc17xx/ldscript
new file mode 100644
index 0000000..f50b993
--- /dev/null
+++ b/arch/arm/lpc17xx/ldscript
@@ -0,0 +1,210 @@
+/* Linker script for Cortex-M3
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ *  Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+/*ENTRY(_start)*/
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
+
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
+  ram (rwx) : ORIGIN = 0x10000000, LENGTH =  32K
+  
+  ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16k
+  ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16k
+  ram3(rwx) : ORIGIN = 0x40038000, LENGTH = 2k
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __cs3_region_start_rom = .;
+    *(.cs3.region-head.rom)
+    __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+    *(.cs3.interrupt_vector)
+    /* Make sure we pulled in an interrupt vector.  */
+    ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+    *(.rom)
+    *(.rom.b)
+
+    __cs3_reset = __cs3_reset_cortex_m;
+    *(.cs3.reset)
+    /* Make sure we pulled in some reset code.  */
+    ASSERT (. != __cs3_reset, "No reset code");
+
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    . = ALIGN(4);
+    KEEP(*(.init))
+
+    . = ALIGN(4);
+    __preinit_array_start = .;
+    KEEP (*(.preinit_array))
+    __preinit_array_end = .;
+
+    . = ALIGN(4);
+    __init_array_start = .;
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    __init_array_end = .;
+
+    . = ALIGN(0x4);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+
+    . = ALIGN(4);
+    KEEP(*(.fini))
+
+    . = ALIGN(4);
+    __fini_array_start = .;
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    __fini_array_end = .;
+
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    . = ALIGN(4);
+    __cs3_regions = .;
+    LONG (0)
+    LONG (__cs3_region_init_ram)
+    LONG (__cs3_region_start_ram)
+    LONG (__cs3_region_init_size_ram)
+    LONG (__cs3_region_zero_size_ram)
+  }
+
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >rom
+  __exidx_end = .;
+  .text.align :
+  {
+    . = ALIGN(8);
+    _etext = .;
+  } >rom
+  __cs3_region_size_rom = LENGTH(rom);
+  __cs3_region_num = 1;
+
+  .data :
+  {
+    __cs3_region_start_ram = .;
+    *(.cs3.region-head.ram)
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    *(.ram)
+    . = ALIGN (8);
+    _edata = .;
+  } >ram AT>rom
+  .bss :
+  {
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    *(.ram.b)
+    . = ALIGN (8);
+    _end = .;
+    __end = .;
+  } >ram AT>rom
+  /* This used for USB RAM section */
+	.usb_ram (NOLOAD):
+	{
+		*.o (USB_RAM)
+	} > ram2
+  .heap (NOLOAD) :
+  {
+    *(.heap)
+  } >ram
+  .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
+  {
+    *(.stack)
+    _estack = .;
+    PROVIDE(estack = .);
+  } >ram
+
+  __cs3_region_init_ram = LOADADDR (.data);
+  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+  __cs3_region_zero_size_ram = _end - _edata;
+  __cs3_region_size_ram = LENGTH(ram);
+  __cs3_region_num = 1;
+
+  .stab 0 (NOLOAD) : { *(.stab) }
+  .stabstr 0 (NOLOAD) : { *(.stabstr) }
+  /* DWARF debug sections.
+   * Symbols in the DWARF debugging sections are relative to the beginning
+   * of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/arch/arm/lpc17xx/startup.s b/arch/arm/lpc17xx/startup.s
new file mode 100644
index 0000000..b195a18
--- /dev/null
+++ b/arch/arm/lpc17xx/startup.s
@@ -0,0 +1,243 @@
+/*****************************************************************************/
+/* startup_LPC17xx.s: Startup file for LPC17xx device series                 */
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+
+/*
+//*** <<< Use Configuration Wizard in Context Menu >>> ***
+*/
+
+
+/*
+// <h> Stack Configuration
+//   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+    .equ    Stack_Size, 0x00000100
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+// <h> Heap Configuration
+//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+    .equ    Heap_Size,  0x00001000
+
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   WDT_IRQHandler              /* 16: Watchdog Timer               */
+    .long   TIMER0_IRQHandler           /* 17: Timer0                       */
+    .long   TIMER1_IRQHandler           /* 18: Timer1                       */
+    .long   TIMER2_IRQHandler           /* 19: Timer2                       */
+    .long   TIMER3_IRQHandler           /* 20: Timer3                       */
+    .long   UART0_IRQHandler            /* 21: UART0                        */
+    .long   UART1_IRQHandler            /* 22: UART1                        */
+    .long   UART2_IRQHandler            /* 23: UART2                        */
+    .long   UART3_IRQHandler            /* 24: UART3                        */
+    .long   PWM1_IRQHandler             /* 25: PWM1                         */
+    .long   I2C0_IRQHandler             /* 26: I2C0                         */
+    .long   I2C1_IRQHandler             /* 27: I2C1                         */
+    .long   I2C2_IRQHandler             /* 28: I2C2                         */
+    .long   SPI_IRQHandler              /* 29: SPI                          */
+    .long   SSP0_IRQHandler             /* 30: SSP0                         */
+    .long   SSP1_IRQHandler             /* 31: SSP1                         */
+    .long   PLL0_IRQHandler             /* 32: PLL0 Lock (Main PLL)         */
+    .long   RTC_IRQHandler              /* 33: Real Time Clock              */
+    .long   EINT0_IRQHandler            /* 34: External Interrupt 0         */
+    .long   EINT1_IRQHandler            /* 35: External Interrupt 1         */
+    .long   EINT2_IRQHandler            /* 36: External Interrupt 2         */
+    .long   EINT3_IRQHandler            /* 37: External Interrupt 3         */
+    .long   ADC_IRQHandler              /* 38: A/D Converter                */
+    .long   BOD_IRQHandler              /* 39: Brown-Out Detect             */
+    .long   USB_IRQHandler              /* 40: USB                          */
+    .long   CAN_IRQHandler              /* 41: CAN                          */
+    .long   DMA_IRQHandler              /* 42: General Purpose DMA          */
+    .long   I2S_IRQHandler              /* 43: I2S                          */
+    .long   ENET_IRQHandler             /* 44: Ethernet                     */
+    .long   RIT_IRQHandler              /* 45: Repetitive Interrupt Timer   */
+    .long   MCPWM_IRQHandler            /* 46: Motor Control PWM            */
+    .long   QEI_IRQHandler              /* 47: Quadrature Encoder Interface */
+    .long   PLL1_IRQHandler             /* 48: PLL1 Lock (USB PLL)          */
+    .long   USBActivity_IRQHandler      /* 49: USB Activity                 */
+    .long   CANActivity_IRQHandler      /* 50: CAN Activity                 */
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     WDT_IRQHandler
+    IRQ     TIMER0_IRQHandler
+    IRQ     TIMER1_IRQHandler
+    IRQ     TIMER2_IRQHandler
+    IRQ     TIMER3_IRQHandler
+    IRQ     UART0_IRQHandler
+    IRQ     UART1_IRQHandler
+    IRQ     UART2_IRQHandler
+    IRQ     UART3_IRQHandler
+    IRQ     PWM1_IRQHandler
+    IRQ     I2C0_IRQHandler
+    IRQ     I2C1_IRQHandler
+    IRQ     I2C2_IRQHandler
+    IRQ     SPI_IRQHandler
+    IRQ     SSP0_IRQHandler
+    IRQ     SSP1_IRQHandler
+    IRQ     PLL0_IRQHandler
+    IRQ     RTC_IRQHandler
+    IRQ     EINT0_IRQHandler
+    IRQ     EINT1_IRQHandler
+    IRQ     EINT2_IRQHandler
+    IRQ     EINT3_IRQHandler
+    IRQ     ADC_IRQHandler
+    IRQ     BOD_IRQHandler
+    IRQ     USB_IRQHandler
+    IRQ     CAN_IRQHandler
+    IRQ     DMA_IRQHandler
+    IRQ     I2S_IRQHandler
+    IRQ     ENET_IRQHandler
+    IRQ     RIT_IRQHandler
+    IRQ     MCPWM_IRQHandler
+    IRQ     QEI_IRQHandler
+    IRQ     PLL1_IRQHandler
+    IRQ     USBActivity_IRQHandler
+    IRQ     CANActivity_IRQHandler
+
+    .end