diff options
Diffstat (limited to 'FreeRTOS/Source/portable/GCC')
| -rw-r--r-- | FreeRTOS/Source/portable/GCC/ARM_CM3/port.c | 283 | ||||
| -rw-r--r-- | FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h | 156 | ||||
| -rw-r--r-- | FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c | 1101 | ||||
| -rw-r--r-- | FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h | 199 |
4 files changed, 1739 insertions, 0 deletions
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c new file mode 100644 index 0000000..fa24c7f --- /dev/null +++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c @@ -0,0 +1,283 @@ +/*
+ FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
+
+ ***************************************************************************
+ * *
+ * If you are: *
+ * *
+ * + New to FreeRTOS, *
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *
+ * + Looking for basic training, *
+ * + Wanting to improve your FreeRTOS skills and productivity *
+ * *
+ * then take a look at the FreeRTOS books - available as PDF or paperback *
+ * *
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
+ * http://www.FreeRTOS.org/Documentation *
+ * *
+ * A pdf reference manual is also available. Both are usually delivered *
+ * to your inbox within 20 minutes to two hours when purchased between 8am *
+ * and 8pm GMT (although please allow up to 24 hours in case of *
+ * exceptional circumstances). Thank you for your support! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ ***NOTE*** The exception to the GPL is included to allow you to distribute
+ a combined work that includes FreeRTOS without being obliged to provide the
+ source code for proprietary components outside of the FreeRTOS kernel.
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+defined. The value should also ensure backward compatibility.
+FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+ #define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 )
+#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 )
+#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK 0x00000004
+#define portNVIC_SYSTICK_INT 0x00000002
+#define portNVIC_SYSTICK_ENABLE 0x00000001
+#define portNVIC_PENDSVSET 0x10000000
+#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
+#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+/* The priority used by the kernel is assigned to a variable to make access
+from inline assembler easier. */
+const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+void vPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ interrupt. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = 0; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ __asm volatile (
+ " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
+ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+ " msr psp, r0 \n" /* Restore the task stack pointer. */
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " orr r14, #0xd \n"
+ " bx r14 \n"
+ " \n"
+ " .align 2 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortStartFirstTask( void )
+{
+ __asm volatile(
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
+ " cpsie i \n" /* Globally enable interrupts. */
+ " svc 0 \n" /* System call to start first task. */
+ " nop \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+portBASE_TYPE xPortStartScheduler( void )
+{
+ /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
+ *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
+ *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Start the first task. */
+ vPortStartFirstTask();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the CM3 port will require this function as there
+ is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldFromISR( void )
+{
+ /* Set a PendSV to request a context switch. */
+ *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ uxCriticalNesting--;
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " mrs r0, psp \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
+ " \n"
+ " stmdb sp!, {r3, r14} \n"
+ " mov r0, %0 \n"
+ " msr basepri, r0 \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldmia sp!, {r3, r14} \n"
+ " \n" /* Restore the context, including the critical nesting count. */
+ " ldr r1, [r3] \n"
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers. */
+ " msr psp, r0 \n"
+ " bx r14 \n"
+ " \n"
+ " .align 2 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+unsigned long ulDummy;
+
+ /* If using preemption, also force a context switch. */
+ #if configUSE_PREEMPTION == 1
+ *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+ #endif
+
+ ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ vTaskIncrementTick();
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+ /* Configure SysTick to interrupt at the requested rate. */
+ *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h new file mode 100644 index 0000000..3a106d5 --- /dev/null +++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h @@ -0,0 +1,156 @@ +/*
+ FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
+
+ ***************************************************************************
+ * *
+ * If you are: *
+ * *
+ * + New to FreeRTOS, *
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *
+ * + Looking for basic training, *
+ * + Wanting to improve your FreeRTOS skills and productivity *
+ * *
+ * then take a look at the FreeRTOS books - available as PDF or paperback *
+ * *
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
+ * http://www.FreeRTOS.org/Documentation *
+ * *
+ * A pdf reference manual is also available. Both are usually delivered *
+ * to your inbox within 20 minutes to two hours when purchased between 8am *
+ * and 8pm GMT (although please allow up to 24 hours in case of *
+ * exceptional circumstances). Thank you for your support! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ ***NOTE*** The exception to the GPL is included to allow you to distribute
+ a combined work that includes FreeRTOS without being obliged to provide the
+ source code for proprietary components outside of the FreeRTOS kernel.
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE unsigned portLONG
+#define portBASE_TYPE long
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef unsigned portSHORT portTickType;
+ #define portMAX_DELAY ( portTickType ) 0xffff
+#else
+ typedef unsigned portLONG portTickType;
+ #define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vPortYieldFromISR( void );
+
+#define portYIELD() vPortYieldFromISR()
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other
+ * registers. r0 is clobbered.
+ */
+#define portSET_INTERRUPT_MASK() \
+ __asm volatile \
+ ( \
+ " mov r0, %0 \n" \
+ " msr basepri, r0 \n" \
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY):"r0" \
+ )
+
+/*
+ * Set basepri back to 0 without effective other registers.
+ * r0 is clobbered.
+ */
+#define portCLEAR_INTERRUPT_MASK() \
+ __asm volatile \
+ ( \
+ " mov r0, #0 \n" \
+ " msr basepri, r0 \n" \
+ :::"r0" \
+ )
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK()
+#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portNOP()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c new file mode 100644 index 0000000..66dd5ba --- /dev/null +++ b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c @@ -0,0 +1,1101 @@ +/*
+ FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
+
+ ***************************************************************************
+ * *
+ * If you are: *
+ * *
+ * + New to FreeRTOS, *
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *
+ * + Looking for basic training, *
+ * + Wanting to improve your FreeRTOS skills and productivity *
+ * *
+ * then take a look at the FreeRTOS books - available as PDF or paperback *
+ * *
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
+ * http://www.FreeRTOS.org/Documentation *
+ * *
+ * A pdf reference manual is also available. Both are usually delivered *
+ * to your inbox within 20 minutes to two hours when purchased between 8am *
+ * and 8pm GMT (although please allow up to 24 hours in case of *
+ * exceptional circumstances). Thank you for your support! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ ***NOTE*** The exception to the GPL is included to allow you to distribute
+ a combined work that includes FreeRTOS without being obliged to provide the
+ source code for proprietary components outside of the FreeRTOS kernel.
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Constants required to access and manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long * ) 0xe000e014 )
+#define portNVIC_SYSPRI2 ( ( volatile unsigned long * ) 0xe000ed20 )
+#define portNVIC_SYSPRI1 ( ( volatile unsigned long * ) 0xe000ed1c )
+#define portNVIC_SYS_CTRL_STATE ( ( volatile unsigned long * ) 0xe000ed24 )
+#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE ( ( volatile unsigned long * ) 0xe000ed90 )
+#define portMPU_REGION_BASE_ADDRESS ( ( volatile unsigned long * ) 0xe000ed9C )
+#define portMPU_REGION_ATTRIBUTE ( ( volatile unsigned long * ) 0xe000edA0 )
+#define portMPU_CTRL ( ( volatile unsigned long * ) 0xe000ed94 )
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portMPU_ENABLE ( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
+#define portMPU_REGION_VALID ( 0x10UL )
+#define portMPU_REGION_ENABLE ( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS 0x40000000UL
+#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
+
+/* Constants required to access and manipulate the SysTick. */
+#define portNVIC_SYSTICK_CLK ( 0x00000004UL )
+#define portNVIC_SYSTICK_INT ( 0x00000002UL )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
+#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000 )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC ( 6 )
+
+/* Set the privilege level to user mode if xRunningPrivileged is false. */
+#define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0" :::"r0" )
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. Note this is not saved as part of the task context as context
+switches can only occur when uxCriticalNesting is zero. */
+static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into. The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Checks to see if being called from the context of an unprivileged task, and
+ * if so raises the privilege level and returns false - otherwise does nothing
+ * other than return true.
+ */
+static portBASE_TYPE prvRaisePrivilege( void ) __attribute__(( naked ));
+
+/*
+ * Standard FreeRTOS exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+void xPortSysTickHandler( void ) __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
+void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/*
+ * Starts the scheduler by restoring the context of the first task to run.
+ */
+static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/*
+ * C portion of the SVC handler. The SVC handler is split between an asm entry
+ * and a C wrapper for simplicity of coding and maintenance.
+ */
+static void prvSVCHandler( unsigned long *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
+
+/*
+ * Prototypes for all the MPU wrappers.
+ */
+signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions );
+void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions );
+void MPU_vTaskDelete( xTaskHandle pxTaskToDelete );
+void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement );
+void MPU_vTaskDelay( portTickType xTicksToDelay );
+unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask );
+void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
+void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend );
+signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask );
+void MPU_vTaskResume( xTaskHandle pxTaskToResume );
+void MPU_vTaskSuspendAll( void );
+signed portBASE_TYPE MPU_xTaskResumeAll( void );
+portTickType MPU_xTaskGetTickCount( void );
+unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void );
+void MPU_vTaskList( signed char *pcWriteBuffer );
+void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer );
+void MPU_vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize );
+unsigned long MPU_ulTaskEndTrace( void );
+void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue );
+pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask );
+portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter );
+unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask );
+xTaskHandle MPU_xTaskGetCurrentTaskHandle( void );
+portBASE_TYPE MPU_xTaskGetSchedulerState( void );
+xQueueHandle MPU_xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize );
+signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );
+unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue );
+signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );
+xQueueHandle MPU_xQueueCreateMutex( void );
+xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount );
+portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime );
+portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex );
+signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );
+signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );
+void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName );
+void *MPU_pvPortMalloc( size_t xSize );
+void MPU_vPortFree( void *pv );
+void MPU_vPortInitialiseBlocks( void );
+size_t MPU_xPortGetFreeHeapSize( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ interrupt. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = 0; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+ }
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ /* Assumes psp was in use. */
+ __asm volatile
+ (
+ #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ #else
+ " mrs r0, psp \n"
+ #endif
+ " b prvSVCHandler \n"
+ :::"r0"
+ );
+
+ /* This will never get executed, but is required to prevent prvSVCHandler
+ being removed by the optimiser. */
+ prvSVCHandler( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSVCHandler( unsigned long *pulParam )
+{
+unsigned char ucSVCNumber;
+
+ /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
+ xPSR. The first argument (r0) is pulParam[ 0 ]. */
+ ucSVCNumber = ( ( unsigned char * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
+ switch( ucSVCNumber )
+ {
+ case portSVC_START_SCHEDULER : *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI;
+ prvRestoreContextOfFirstTask();
+ break;
+
+ case portSVC_YIELD : *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+ break;
+
+ case portSVC_RAISE_PRIVILEGE : __asm volatile
+ (
+ " mrs r1, control \n" /* Obtain current control value. */
+ " bic r1, #1 \n" /* Set privilege bit. */
+ " msr control, r1 \n" /* Write back new control value. */
+ :::"r1"
+ );
+ break;
+
+ default : /* Unknown SVC call. */
+ break;
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvRestoreContextOfFirstTask( void )
+{
+ __asm volatile
+ (
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
+ " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
+ " ldr r1, [r3] \n"
+ " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
+ " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
+ " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
+ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
+ " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
+ " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */
+ " msr control, r3 \n"
+ " msr psp, r0 \n" /* Restore the task stack pointer. */
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldr r14, =0xfffffffd \n" /* Load exec return code. */
+ " bx r14 \n"
+ " \n"
+ " .align 2 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+portBASE_TYPE xPortStartScheduler( void )
+{
+ /* Make PendSV and SysTick the same priroity as the kernel. */
+ *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
+ *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
+
+ /* Configure the regions in the MPU that are common to all tasks. */
+ prvSetupMPU();
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Start the first task. */
+ __asm volatile( " svc %0 \n"
+ :: "i" (portSVC_START_SCHEDULER) );
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* It is unlikely that the CM3 port will require this function as there
+ is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+
+ portRESET_PRIVILEGE( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ uxCriticalNesting--;
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ portRESET_PRIVILEGE( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " mrs r0, psp \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " mrs r1, control \n"
+ " stmdb r0!, {r1, r4-r11} \n" /* Save the remaining registers. */
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
+ " \n"
+ " stmdb sp!, {r3, r14} \n"
+ " mov r0, %0 \n"
+ " msr basepri, r0 \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldmia sp!, {r3, r14} \n"
+ " \n" /* Restore the context. */
+ " ldr r1, [r3] \n"
+ " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
+ " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
+ " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
+ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
+ " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
+ " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */
+ " msr control, r3 \n"
+ " \n"
+ " msr psp, r0 \n"
+ " bx r14 \n"
+ " \n"
+ " .align 2 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+unsigned long ulDummy;
+
+ /* If using preemption, also force a context switch. */
+ #if configUSE_PREEMPTION == 1
+ *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+ #endif
+
+ ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ vTaskIncrementTick();
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+ /* Configure SysTick to interrupt at the requested rate. */
+ *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+extern unsigned long __privileged_functions_end__[];
+extern unsigned long __FLASH_segment_start__[];
+extern unsigned long __FLASH_segment_end__[];
+extern unsigned long __privileged_data_start__[];
+extern unsigned long __privileged_data_end__[];
+
+ /* Check the expected MPU is present. */
+ if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* First setup the entire flash for unprivileged read only access. */
+ *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portUNPRIVILEGED_FLASH_REGION );
+
+ *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_READ_ONLY ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( prvGetMPURegionSizeSetting( ( unsigned long ) __FLASH_segment_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Setup the first 16K for privileged only access (even though less
+ than 10K is actually being used). This is where the kernel code is
+ placed. */
+ *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portPRIVILEGED_FLASH_REGION );
+
+ *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_functions_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Setup the privileged data RAM region. This is where the kernel data
+ is placed. */
+ *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portPRIVILEGED_RAM_REGION );
+
+ *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* By default allow everything to access the general peripherals. The
+ system peripherals and registers are protected. */
+ *portMPU_REGION_BASE_ADDRESS = ( portPERIPHERALS_START_ADDRESS ) |
+ ( portMPU_REGION_VALID ) |
+ ( portGENERAL_PERIPHERALS_REGION );
+
+ *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+ ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Enable the memory fault exception. */
+ *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE;
+
+ /* Enable the MPU with the background region configured. */
+ *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes )
+{
+unsigned long ulRegionSize, ulReturnValue = 4;
+
+ /* 32 is the smallest region size, 31 is the largest valid value for
+ ulReturnValue. */
+ for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+ {
+ if( ulActualSizeInBytes <= ulRegionSize )
+ {
+ break;
+ }
+ else
+ {
+ ulReturnValue++;
+ }
+ }
+
+ /* Shift the code by one before returning so it can be written directly
+ into the the correct bit position of the attribute register. */
+ return ( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRaisePrivilege( void )
+{
+ __asm volatile
+ (
+ " mrs r0, control \n"
+ " tst r0, #1 \n" /* Is the task running privileged? */
+ " itte ne \n"
+ " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */
+ " svcne %0 \n" /* Switch to privileged. */
+ " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
+ " bx lr \n"
+ :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"
+ );
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth )
+{
+extern unsigned long __SRAM_segment_start__[];
+extern unsigned long __SRAM_segment_end__[];
+extern unsigned long __privileged_data_start__[];
+extern unsigned long __privileged_data_end__[];
+long lIndex;
+unsigned long ul;
+
+ if( xRegions == NULL )
+ {
+ /* No MPU regions are specified so allow access to all RAM. */
+ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+ ( ( unsigned long ) __SRAM_segment_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portSTACK_REGION );
+
+ xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( prvGetMPURegionSizeSetting( ( unsigned long ) __SRAM_segment_end__ - ( unsigned long ) __SRAM_segment_start__ ) ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
+ just removed the privileged only parameters. */
+ xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
+ ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */
+ ( portMPU_REGION_VALID ) |
+ ( portSTACK_REGION + 1 );
+
+ xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |
+ ( portMPU_REGION_ENABLE );
+
+ /* Invalidate all other regions. */
+ for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ {
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+ }
+ }
+ else
+ {
+ /* This function is called automatically when the task is created - in
+ which case the stack region parameters will be valid. At all other
+ times the stack parameters will not be valid and it is assumed that the
+ stack region has already been configured. */
+ if( usStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+ ( ( unsigned long ) pxBottomOfStack ) |
+ ( portMPU_REGION_VALID ) |
+ ( portSTACK_REGION ); /* Region number. */
+
+ xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+ ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+ ( prvGetMPURegionSizeSetting( ( unsigned long ) usStackDepth * ( unsigned long ) sizeof( portSTACK_TYPE ) ) ) |
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( portMPU_REGION_ENABLE );
+ }
+
+ lIndex = 0;
+
+ for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ {
+ if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+ {
+ /* Translate the generic region definition contained in
+ xRegions into the CM3 specific MPU settings that are then
+ stored in xMPUSettings. */
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+ ( ( unsigned long ) xRegions[ lIndex ].pvBaseAddress ) |
+ ( portMPU_REGION_VALID ) |
+ ( portSTACK_REGION + ul ); /* Region number. */
+
+ xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+ ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+ ( xRegions[ lIndex ].ulParameters ) |
+ ( portMPU_REGION_ENABLE );
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions )
+{
+signed portBASE_TYPE xReturn;
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions )
+{
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskAllocateMPURegions( xTask, xRegions );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+ void MPU_vTaskDelete( xTaskHandle pxTaskToDelete )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskDelete( pxTaskToDelete );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+ void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+ void MPU_vTaskDelay( portTickType xTicksToDelay )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskDelay( xTicksToDelay );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+ unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask )
+ {
+ unsigned portBASE_TYPE uxReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ uxReturn = uxTaskPriorityGet( pxTask );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return uxReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+ void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskPrioritySet( pxTask, uxNewPriority );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+ void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskSuspend( pxTaskToSuspend );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+ signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask )
+ {
+ signed portBASE_TYPE xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xTaskIsTaskSuspended( xTask );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+ void MPU_vTaskResume( xTaskHandle pxTaskToResume )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskResume( pxTaskToResume );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+void MPU_vTaskSuspendAll( void )
+{
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskSuspendAll();
+ portRESET_PRIVILEGE( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE MPU_xTaskResumeAll( void )
+{
+signed portBASE_TYPE xReturn;
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xTaskResumeAll();
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+portTickType MPU_xTaskGetTickCount( void )
+{
+portTickType xReturn;
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xTaskGetTickCount();
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void )
+{
+unsigned portBASE_TYPE uxReturn;
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ uxReturn = uxTaskGetNumberOfTasks();
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+ void MPU_vTaskList( signed char *pcWriteBuffer )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskList( pcWriteBuffer );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+ void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskGetRunTimeStats( pcWriteBuffer );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+ void MPU_vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskStartTrace( pcBuffer, ulBufferSize );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+ unsigned long MPU_ulTaskEndTrace( void )
+ {
+ unsigned long ulReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ ulReturn = ulTaskEndTrace();
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return ulReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vTaskSetApplicationTaskTag( xTask, pxTagValue );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask )
+ {
+ pdTASK_HOOK_CODE xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xTaskGetApplicationTaskTag( xTask );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter )
+ {
+ portBASE_TYPE xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+ unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask )
+ {
+ unsigned portBASE_TYPE uxReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ uxReturn = uxTaskGetStackHighWaterMark( xTask );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return uxReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )
+ xTaskHandle MPU_xTaskGetCurrentTaskHandle( void )
+ {
+ xTaskHandle xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xTaskGetCurrentTaskHandle();
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+ portBASE_TYPE MPU_xTaskGetSchedulerState( void )
+ {
+ portBASE_TYPE xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xTaskGetSchedulerState();
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+xQueueHandle MPU_xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize )
+{
+xQueueHandle xReturn;
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xQueueCreate( uxQueueLength, uxItemSize );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )
+{
+signed portBASE_TYPE xReturn;
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue )
+{
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+unsigned portBASE_TYPE uxReturn;
+
+ uxReturn = uxQueueMessagesWaiting( pxQueue );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )
+{
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+signed portBASE_TYPE xReturn;
+
+ xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+ xQueueHandle MPU_xQueueCreateMutex( void )
+ {
+ xQueueHandle xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xQueueCreateMutex();
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if configUSE_COUNTING_SEMAPHORES == 1
+ xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount )
+ {
+ xQueueHandle xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xQueueHandle xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+ portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime )
+ {
+ portBASE_TYPE xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+ portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex )
+ {
+ portBASE_TYPE xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xQueueGiveMutexRecursive( xMutex );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if configUSE_ALTERNATIVE_API == 1
+ signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )
+ {
+ signed portBASE_TYPE xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = signed portBASE_TYPE xQueueAltGenericSend( pxQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if configUSE_ALTERNATIVE_API == 1
+ signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )
+ {
+ signed portBASE_TYPE xReturn;
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xQueueAltGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if configQUEUE_REGISTRY_SIZE > 0
+ void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName )
+ {
+ portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vQueueAddToRegistry( xQueue, pcName );
+
+ portRESET_PRIVILEGE( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+void *MPU_pvPortMalloc( size_t xSize )
+{
+void *pvReturn;
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ pvReturn = pvPortMalloc( xSize );
+
+ portRESET_PRIVILEGE( xRunningPrivileged );
+
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void MPU_vPortFree( void *pv )
+{
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vPortFree( pv );
+
+ portRESET_PRIVILEGE( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void MPU_vPortInitialiseBlocks( void )
+{
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ vPortInitialiseBlocks();
+
+ portRESET_PRIVILEGE( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xPortGetFreeHeapSize( void )
+{
+size_t xReturn;
+portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();
+
+ xReturn = xPortGetFreeHeapSize();
+
+ portRESET_PRIVILEGE( xRunningPrivileged );
+
+ return xReturn;
+}
+
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h new file mode 100644 index 0000000..2ce7d12 --- /dev/null +++ b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h @@ -0,0 +1,199 @@ +/*
+ FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
+
+ ***************************************************************************
+ * *
+ * If you are: *
+ * *
+ * + New to FreeRTOS, *
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *
+ * + Looking for basic training, *
+ * + Wanting to improve your FreeRTOS skills and productivity *
+ * *
+ * then take a look at the FreeRTOS books - available as PDF or paperback *
+ * *
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
+ * http://www.FreeRTOS.org/Documentation *
+ * *
+ * A pdf reference manual is also available. Both are usually delivered *
+ * to your inbox within 20 minutes to two hours when purchased between 8am *
+ * and 8pm GMT (although please allow up to 24 hours in case of *
+ * exceptional circumstances). Thank you for your support! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ ***NOTE*** The exception to the GPL is included to allow you to distribute
+ a combined work that includes FreeRTOS without being obliged to provide the
+ source code for proprietary components outside of the FreeRTOS kernel.
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE unsigned portLONG
+#define portBASE_TYPE long
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef unsigned portSHORT portTickType;
+ #define portMAX_DELAY ( portTickType ) 0xffff
+#else
+ typedef unsigned portLONG portTickType;
+ #define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+#define portUSING_MPU_WRAPPERS 1
+#define portPRIVILEGE_BIT ( 0x80000000UL )
+
+#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
+
+#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
+#define portPRIVILEGED_FLASH_REGION ( 1UL )
+#define portPRIVILEGED_RAM_REGION ( 2UL )
+#define portGENERAL_PERIPHERALS_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" )
+
+typedef struct MPU_REGION_REGISTERS
+{
+ unsigned portLONG ulRegionBaseAddress;
+ unsigned portLONG ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+typedef struct MPU_SETTINGS
+{
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+#define portSVC_START_SCHEDULER 0
+#define portSVC_YIELD 1
+#define portSVC_RAISE_PRIVILEGE 2
+
+/* Scheduler utilities. */
+
+#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) )
+#define portYIELD_WITHIN_API() *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET
+
+#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 )
+#define portNVIC_PENDSVSET 0x10000000
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other
+ * registers. r0 is clobbered.
+ */
+#define portSET_INTERRUPT_MASK() \
+ __asm volatile \
+ ( \
+ " mov r0, %0 \n" \
+ " msr basepri, r0 \n" \
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY):"r0" \
+ )
+
+/*
+ * Set basepri back to 0 without effective other registers.
+ * r0 is clobbered.
+ */
+#define portCLEAR_INTERRUPT_MASK() \
+ __asm volatile \
+ ( \
+ " mov r0, #0 \n" \
+ " msr basepri, r0 \n" \
+ :::"r0" \
+ )
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK()
+#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK()
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portNOP()
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
|