diff options
Diffstat (limited to 'arch/arm/lpc17xx/Drivers/include')
26 files changed, 8012 insertions, 0 deletions
diff --git a/arch/arm/lpc17xx/Drivers/include/debug_frmwrk.h b/arch/arm/lpc17xx/Drivers/include/debug_frmwrk.h new file mode 100644 index 0000000..b7b56f8 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/debug_frmwrk.h @@ -0,0 +1,69 @@ +/***********************************************************************//**
+ * @file debug_frmwrk.h
+ * @brief Contains some utilities that used for debugging through UART
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ *----------------------------------------------------------------------------
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+#ifndef DEBUG_FRMWRK_H_
+#define DEBUG_FRMWRK_H_
+
+//#include <stdarg.h>
+#include "lpc17xx_uart.h"
+
+#define USED_UART_DEBUG_PORT 0
+
+#if (USED_UART_DEBUG_PORT==0)
+#define DEBUG_UART_PORT LPC_UART0
+#elif (USED_UART_DEBUG_PORT==1)
+#define DEBUG_UART_PORT LPC_UART1
+#endif
+
+#define _DBG(x) _db_msg(DEBUG_UART_PORT, x)
+#define _DBG_(x) _db_msg_(DEBUG_UART_PORT, x)
+#define _DBC(x) _db_char(DEBUG_UART_PORT, x)
+#define _DBD(x) _db_dec(DEBUG_UART_PORT, x)
+#define _DBD16(x) _db_dec_16(DEBUG_UART_PORT, x)
+#define _DBD32(x) _db_dec_32(DEBUG_UART_PORT, x)
+#define _DBH(x) _db_hex(DEBUG_UART_PORT, x)
+#define _DBH16(x) _db_hex_16(DEBUG_UART_PORT, x)
+#define _DBH32(x) _db_hex_32(DEBUG_UART_PORT, x)
+#define _DG _db_get_char(DEBUG_UART_PORT)
+//void _printf (const char *format, ...);
+
+extern void (*_db_msg)(LPC_UART_TypeDef *UARTx, const void *s);
+extern void (*_db_msg_)(LPC_UART_TypeDef *UARTx, const void *s);
+extern void (*_db_char)(LPC_UART_TypeDef *UARTx, uint8_t ch);
+extern void (*_db_dec)(LPC_UART_TypeDef *UARTx, uint8_t decn);
+extern void (*_db_dec_16)(LPC_UART_TypeDef *UARTx, uint16_t decn);
+extern void (*_db_dec_32)(LPC_UART_TypeDef *UARTx, uint32_t decn);
+extern void (*_db_hex)(LPC_UART_TypeDef *UARTx, uint8_t hexn);
+extern void (*_db_hex_16)(LPC_UART_TypeDef *UARTx, uint16_t hexn);
+extern void (*_db_hex_32)(LPC_UART_TypeDef *UARTx, uint32_t hexn);
+extern uint8_t (*_db_get_char)(LPC_UART_TypeDef *UARTx);
+
+void UARTPutChar (LPC_UART_TypeDef *UARTx, uint8_t ch);
+void UARTPuts(LPC_UART_TypeDef *UARTx, const void *str);
+void UARTPuts_(LPC_UART_TypeDef *UARTx, const void *str);
+void UARTPutDec(LPC_UART_TypeDef *UARTx, uint8_t decnum);
+void UARTPutDec16(LPC_UART_TypeDef *UARTx, uint16_t decnum);
+void UARTPutDec32(LPC_UART_TypeDef *UARTx, uint32_t decnum);
+void UARTPutHex (LPC_UART_TypeDef *UARTx, uint8_t hexnum);
+void UARTPutHex16 (LPC_UART_TypeDef *UARTx, uint16_t hexnum);
+void UARTPutHex32 (LPC_UART_TypeDef *UARTx, uint32_t hexnum);
+uint8_t UARTGetChar (LPC_UART_TypeDef *UARTx);
+void debug_frmwrk_init(void);
+
+#endif /* DEBUG_FRMWRK_H_ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_adc.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_adc.h new file mode 100644 index 0000000..377dd7c --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_adc.h @@ -0,0 +1,288 @@ +/***********************************************************************//**
+ * @file lpc17xx_adc.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for ADC firmware library on LPC17xx
+ * @version 3.0
+ * @date 18. June. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup ADC ADC
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_ADC_H_
+#define LPC17XX_ADC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private macros ------------------------------------------------------------- */
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/* -------------------------- BIT DEFINITIONS ----------------------------------- */
+/*********************************************************************//**
+ * Macro defines for ADC control register
+ **********************************************************************/
+/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CH_SEL(n) ((1UL << n))
+/** The APB clock (PCLK) is divided by (this value plus one)
+* to produce the clock for the A/D */
+#define ADC_CR_CLKDIV(n) ((n<<8))
+/** Repeated conversions A/D enable bit */
+#define ADC_CR_BURST ((1UL<<16))
+/** ADC convert in power down mode */
+#define ADC_CR_PDN ((1UL<<21))
+/** Start mask bits */
+#define ADC_CR_START_MASK ((7UL<<24))
+/** Select Start Mode */
+#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
+/** Start conversion now */
+#define ADC_CR_START_NOW ((1UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */
+#define ADC_CR_START_EINT0 ((2UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */
+#define ADC_CR_START_CAP01 ((3UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on MAT0.1 */
+#define ADC_CR_START_MAT01 ((4UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on MAT0.3 */
+#define ADC_CR_START_MAT03 ((5UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on MAT1.0 */
+#define ADC_CR_START_MAT10 ((6UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on MAT1.1 */
+#define ADC_CR_START_MAT11 ((7UL<<24))
+/** Start conversion on a falling edge on the selected CAP/MAT signal */
+#define ADC_CR_EDGE ((1UL<<27))
+
+/*********************************************************************//**
+ * Macro defines for ADC Global Data register
+ **********************************************************************/
+/** When DONE is 1, this field contains result value of ADC conversion */
+#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
+/** These bits contain the channel from which the LS bits were converted */
+#define ADC_GDR_CH(n) (((n>>24)&0x7))
+/** This bit is 1 in burst mode if the results of one or
+ * more conversions was (were) lost */
+#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
+/** This bit is set to 1 when an A/D conversion completes */
+#define ADC_GDR_DONE_FLAG ((1UL<<31))
+
+/** This bits is used to mask for Channel */
+#define ADC_GDR_CH_MASK ((7UL<<24))
+/*********************************************************************//**
+ * Macro defines for ADC Interrupt register
+ **********************************************************************/
+/** These bits allow control over which A/D channels generate
+ * interrupts for conversion completion */
+#define ADC_INTEN_CH(n) ((1UL<<n))
+/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
+#define ADC_INTEN_GLOBAL ((1UL<<8))
+
+/*********************************************************************//**
+ * Macro defines for ADC Data register
+ **********************************************************************/
+/** When DONE is 1, this field contains result value of ADC conversion */
+#define ADC_DR_RESULT(n) (((n>>4)&0xFFF))
+/** These bits mirror the OVERRRUN status flags that appear in the
+ * result register for each A/D channel */
+#define ADC_DR_OVERRUN_FLAG ((1UL<<30))
+/** This bit is set to 1 when an A/D conversion completes. It is cleared
+ * when this register is read */
+#define ADC_DR_DONE_FLAG ((1UL<<31))
+
+/*********************************************************************//**
+ * Macro defines for ADC Status register
+**********************************************************************/
+/** These bits mirror the DONE status flags that appear in the result
+ * register for each A/D channel */
+#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
+/** These bits mirror the OVERRRUN status flags that appear in the
+ * result register for each A/D channel */
+#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
+/** This bit is the A/D interrupt flag */
+#define ADC_STAT_INT_FLAG ((1UL<<16))
+
+/*********************************************************************//**
+ * Macro defines for ADC Trim register
+**********************************************************************/
+/** Offset trim bits for ADC operation */
+#define ADC_ADCOFFS(n) (((n&0xF)<<4))
+/** Written to boot code*/
+#define ADC_TRIM(n) (((n&0xF)<<8))
+
+/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
+/** Check ADC parameter */
+#define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC))
+
+/** Check ADC state parameter */
+#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING))
+
+/** Check ADC state parameter */
+#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE))
+
+/** Check ADC rate parameter */
+#define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000))
+
+/** Check ADC channel selection parameter */
+#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\
+||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\
+||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\
+||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7))
+
+/** Check ADC start option parameter */
+#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\
+||(OPT == ADC_START_ON_EINT0)||(OPT == ADC_START_ON_CAP01)\
+||(OPT == ADC_START_ON_MAT01)||(OPT == ADC_START_ON_MAT03)\
+||(OPT == ADC_START_ON_MAT10)||(OPT == ADC_START_ON_MAT11))
+
+/** Check ADC interrupt type parameter */
+#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\
+||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\
+||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\
+||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\
+||(OPT == ADC_ADGINTEN))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup ADC_Public_Types ADC Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief ADC enumeration
+ **********************************************************************/
+/** @brief Channel Selection */
+typedef enum
+{
+ ADC_CHANNEL_0 = 0, /*!< Channel 0 */
+ ADC_CHANNEL_1, /*!< Channel 1 */
+ ADC_CHANNEL_2, /*!< Channel 2 */
+ ADC_CHANNEL_3, /*!< Channel 3 */
+ ADC_CHANNEL_4, /*!< Channel 4 */
+ ADC_CHANNEL_5, /*!< Channel 5 */
+ ADC_CHANNEL_6, /*!< Channel 6 */
+ ADC_CHANNEL_7 /*!< Channel 7 */
+}ADC_CHANNEL_SELECTION;
+
+/** @brief Type of start option */
+typedef enum
+{
+ ADC_START_CONTINUOUS =0, /*!< Continuous mode */
+ ADC_START_NOW, /*!< Start conversion now */
+ ADC_START_ON_EINT0, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on P2.10/EINT0 */
+ ADC_START_ON_CAP01, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on P1.27/CAP0.1 */
+ ADC_START_ON_MAT01, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on MAT0.1 */
+ ADC_START_ON_MAT03, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on MAT0.3 */
+ ADC_START_ON_MAT10, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on MAT1.0 */
+ ADC_START_ON_MAT11 /*!< Start conversion when the edge selected
+ * by bit 27 occurs on MAT1.1 */
+} ADC_START_OPT;
+
+
+/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
+typedef enum
+{
+ ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
+ *on the selected CAP/MAT signal */
+ ADC_START_ON_FALLING /*!< Start conversion on a falling edge
+ *on the selected CAP/MAT signal */
+} ADC_START_ON_EDGE_OPT;
+
+/** @brief* ADC type interrupt enum */
+typedef enum
+{
+ ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */
+ ADC_ADINTEN1, /*!< Interrupt channel 1 */
+ ADC_ADINTEN2, /*!< Interrupt channel 2 */
+ ADC_ADINTEN3, /*!< Interrupt channel 3 */
+ ADC_ADINTEN4, /*!< Interrupt channel 4 */
+ ADC_ADINTEN5, /*!< Interrupt channel 5 */
+ ADC_ADINTEN6, /*!< Interrupt channel 6 */
+ ADC_ADINTEN7, /*!< Interrupt channel 7 */
+ ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */
+}ADC_TYPE_INT_OPT;
+
+/** @brief ADC Data status */
+typedef enum
+{
+ ADC_DATA_BURST = 0, /*Burst bit*/
+ ADC_DATA_DONE /*Done bit*/
+}ADC_DATA_STATUS;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup ADC_Public_Functions ADC Public Functions
+ * @{
+ */
+/* Init/DeInit ADC peripheral ----------------*/
+void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate);
+void ADC_DeInit(LPC_ADC_TypeDef *ADCx);
+
+/* Enable/Disable ADC functions --------------*/
+void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
+void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
+void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode);
+void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState);
+
+/* Configure ADC functions -------------------*/
+void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption);
+void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
+
+/* Get ADC information functions -------------------*/
+uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel);
+FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType);
+uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx);
+FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_ADC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_can.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_can.h new file mode 100644 index 0000000..7da1b12 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_can.h @@ -0,0 +1,860 @@ +/***********************************************************************//**
+ * @file lpc17xx_can.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for CAN firmware library on LPC17xx
+ * @version 3.0
+ * @date 18. June. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CAN CAN
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_CAN_H_
+#define LPC17XX_CAN_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup CAN_Public_Macros CAN Public Macros
+ * @{
+ */
+#define MSG_ENABLE ((uint8_t)(0))
+#define MSG_DISABLE ((uint8_t)(1))
+#define CAN1_CTRL ((uint8_t)(0))
+#define CAN2_CTRL ((uint8_t)(1))
+#define PARAM_FULLCAN_IC(n) ((n==FULLCAN_IC0)||(n==FULLCAN_IC1))
+#define ID_11 1
+#define MAX_HW_FULLCAN_OBJ 64
+#define MAX_SW_FULLCAN_OBJ 32
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for CAN Mode Register
+ **********************************************************************/
+/** CAN Reset mode */
+#define CAN_MOD_RM ((uint32_t)(1))
+/** CAN Listen Only Mode */
+#define CAN_MOD_LOM ((uint32_t)(1<<1))
+/** CAN Self Test mode */
+#define CAN_MOD_STM ((uint32_t)(1<<2))
+/** CAN Transmit Priority mode */
+#define CAN_MOD_TPM ((uint32_t)(1<<3))
+/** CAN Sleep mode */
+#define CAN_MOD_SM ((uint32_t)(1<<4))
+/** CAN Receive Polarity mode */
+#define CAN_MOD_RPM ((uint32_t)(1<<5))
+/** CAN Test mode */
+#define CAN_MOD_TM ((uint32_t)(1<<7))
+
+/*********************************************************************//**
+ * Macro defines for CAN Command Register
+ **********************************************************************/
+/** CAN Transmission Request */
+#define CAN_CMR_TR ((uint32_t)(1))
+/** CAN Abort Transmission */
+#define CAN_CMR_AT ((uint32_t)(1<<1))
+/** CAN Release Receive Buffer */
+#define CAN_CMR_RRB ((uint32_t)(1<<2))
+/** CAN Clear Data Overrun */
+#define CAN_CMR_CDO ((uint32_t)(1<<3))
+/** CAN Self Reception Request */
+#define CAN_CMR_SRR ((uint32_t)(1<<4))
+/** CAN Select Tx Buffer 1 */
+#define CAN_CMR_STB1 ((uint32_t)(1<<5))
+/** CAN Select Tx Buffer 2 */
+#define CAN_CMR_STB2 ((uint32_t)(1<<6))
+/** CAN Select Tx Buffer 3 */
+#define CAN_CMR_STB3 ((uint32_t)(1<<7))
+
+/*********************************************************************//**
+ * Macro defines for CAN Global Status Register
+ **********************************************************************/
+/** CAN Receive Buffer Status */
+#define CAN_GSR_RBS ((uint32_t)(1))
+/** CAN Data Overrun Status */
+#define CAN_GSR_DOS ((uint32_t)(1<<1))
+/** CAN Transmit Buffer Status */
+#define CAN_GSR_TBS ((uint32_t)(1<<2))
+/** CAN Transmit Complete Status */
+#define CAN_GSR_TCS ((uint32_t)(1<<3))
+/** CAN Receive Status */
+#define CAN_GSR_RS ((uint32_t)(1<<4))
+/** CAN Transmit Status */
+#define CAN_GSR_TS ((uint32_t)(1<<5))
+/** CAN Error Status */
+#define CAN_GSR_ES ((uint32_t)(1<<6))
+/** CAN Bus Status */
+#define CAN_GSR_BS ((uint32_t)(1<<7))
+/** CAN Current value of the Rx Error Counter */
+#define CAN_GSR_RXERR(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Current value of the Tx Error Counter */
+#define CAN_GSR_TXERR(n) ((uint32_t)(n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Interrupt and Capture Register
+ **********************************************************************/
+/** CAN Receive Interrupt */
+#define CAN_ICR_RI ((uint32_t)(1))
+/** CAN Transmit Interrupt 1 */
+#define CAN_ICR_TI1 ((uint32_t)(1<<1))
+/** CAN Error Warning Interrupt */
+#define CAN_ICR_EI ((uint32_t)(1<<2))
+/** CAN Data Overrun Interrupt */
+#define CAN_ICR_DOI ((uint32_t)(1<<3))
+/** CAN Wake-Up Interrupt */
+#define CAN_ICR_WUI ((uint32_t)(1<<4))
+/** CAN Error Passive Interrupt */
+#define CAN_ICR_EPI ((uint32_t)(1<<5))
+/** CAN Arbitration Lost Interrupt */
+#define CAN_ICR_ALI ((uint32_t)(1<<6))
+/** CAN Bus Error Interrupt */
+#define CAN_ICR_BEI ((uint32_t)(1<<7))
+/** CAN ID Ready Interrupt */
+#define CAN_ICR_IDI ((uint32_t)(1<<8))
+/** CAN Transmit Interrupt 2 */
+#define CAN_ICR_TI2 ((uint32_t)(1<<9))
+/** CAN Transmit Interrupt 3 */
+#define CAN_ICR_TI3 ((uint32_t)(1<<10))
+/** CAN Error Code Capture */
+#define CAN_ICR_ERRBIT(n) ((uint32_t)((n&0x1F)<<16))
+/** CAN Error Direction */
+#define CAN_ICR_ERRDIR ((uint32_t)(1<<21))
+/** CAN Error Capture */
+#define CAN_ICR_ERRC(n) ((uint32_t)((n&0x3)<<22))
+/** CAN Arbitration Lost Capture */
+#define CAN_ICR_ALCBIT(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Interrupt Enable Register
+ **********************************************************************/
+/** CAN Receive Interrupt Enable */
+#define CAN_IER_RIE ((uint32_t)(1))
+/** CAN Transmit Interrupt Enable for buffer 1 */
+#define CAN_IER_TIE1 ((uint32_t)(1<<1))
+/** CAN Error Warning Interrupt Enable */
+#define CAN_IER_EIE ((uint32_t)(1<<2))
+/** CAN Data Overrun Interrupt Enable */
+#define CAN_IER_DOIE ((uint32_t)(1<<3))
+/** CAN Wake-Up Interrupt Enable */
+#define CAN_IER_WUIE ((uint32_t)(1<<4))
+/** CAN Error Passive Interrupt Enable */
+#define CAN_IER_EPIE ((uint32_t)(1<<5))
+/** CAN Arbitration Lost Interrupt Enable */
+#define CAN_IER_ALIE ((uint32_t)(1<<6))
+/** CAN Bus Error Interrupt Enable */
+#define CAN_IER_BEIE ((uint32_t)(1<<7))
+/** CAN ID Ready Interrupt Enable */
+#define CAN_IER_IDIE ((uint32_t)(1<<8))
+/** CAN Transmit Enable Interrupt for Buffer 2 */
+#define CAN_IER_TIE2 ((uint32_t)(1<<9))
+/** CAN Transmit Enable Interrupt for Buffer 3 */
+#define CAN_IER_TIE3 ((uint32_t)(1<<10))
+
+/*********************************************************************//**
+ * Macro defines for CAN Bus Timing Register
+ **********************************************************************/
+/** CAN Baudrate Prescaler */
+#define CAN_BTR_BRP(n) ((uint32_t)(n&0x3FF))
+/** CAN Synchronization Jump Width */
+#define CAN_BTR_SJM(n) ((uint32_t)((n&0x3)<<14))
+/** CAN Time Segment 1 */
+#define CAN_BTR_TESG1(n) ((uint32_t)(n&0xF)<<16))
+/** CAN Time Segment 2 */
+#define CAN_BTR_TESG2(n) ((uint32_t)(n&0xF)<<20))
+/** CAN Sampling */
+#define CAN_BTR_SAM(n) ((uint32_t)(1<<23))
+
+/*********************************************************************//**
+ * Macro defines for CAN Error Warning Limit Register
+ **********************************************************************/
+/** CAN Error Warning Limit */
+#define CAN_EWL_EWL(n) ((uint32_t)(n&0xFF))
+
+/*********************************************************************//**
+ * Macro defines for CAN Status Register
+ **********************************************************************/
+/** CAN Receive Buffer Status */
+#define CAN_SR_RBS ((uint32_t)(1))
+/** CAN Data Overrun Status */
+#define CAN_SR_DOS ((uint32_t)(1<<1))
+/** CAN Transmit Buffer Status 1 */
+#define CAN_SR_TBS1 ((uint32_t)(1<<2))
+/** CAN Transmission Complete Status of Buffer 1 */
+#define CAN_SR_TCS1 ((uint32_t)(1<<3))
+/** CAN Receive Status */
+#define CAN_SR_RS ((uint32_t)(1<<4))
+/** CAN Transmit Status 1 */
+#define CAN_SR_TS1 ((uint32_t)(1<<5))
+/** CAN Error Status */
+#define CAN_SR_ES ((uint32_t)(1<<6))
+/** CAN Bus Status */
+#define CAN_SR_BS ((uint32_t)(1<<7))
+/** CAN Transmit Buffer Status 2 */
+#define CAN_SR_TBS2 ((uint32_t)(1<<10))
+/** CAN Transmission Complete Status of Buffer 2 */
+#define CAN_SR_TCS2 ((uint32_t)(1<<11))
+/** CAN Transmit Status 2 */
+#define CAN_SR_TS2 ((uint32_t)(1<<13))
+/** CAN Transmit Buffer Status 2 */
+#define CAN_SR_TBS3 ((uint32_t)(1<<18))
+/** CAN Transmission Complete Status of Buffer 2 */
+#define CAN_SR_TCS3 ((uint32_t)(1<<19))
+/** CAN Transmit Status 2 */
+#define CAN_SR_TS3 ((uint32_t)(1<<21))
+
+/*********************************************************************//**
+ * Macro defines for CAN Receive Frame Status Register
+ **********************************************************************/
+/** CAN ID Index */
+#define CAN_RFS_ID_INDEX(n) ((uint32_t)(n&0x3FF))
+/** CAN Bypass */
+#define CAN_RFS_BP ((uint32_t)(1<<10))
+/** CAN Data Length Code */
+#define CAN_RFS_DLC(n) ((uint32_t)((n&0xF)<<16)
+/** CAN Remote Transmission Request */
+#define CAN_RFS_RTR ((uint32_t)(1<<30))
+/** CAN control 11 bit or 29 bit Identifier */
+#define CAN_RFS_FF ((uint32_t)(1<<31))
+
+/*********************************************************************//**
+ * Macro defines for CAN Receive Identifier Register
+ **********************************************************************/
+/** CAN 11 bit Identifier */
+#define CAN_RID_ID_11(n) ((uint32_t)(n&0x7FF))
+/** CAN 29 bit Identifier */
+#define CAN_RID_ID_29(n) ((uint32_t)(n&0x1FFFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for CAN Receive Data A Register
+ **********************************************************************/
+/** CAN Receive Data 1 */
+#define CAN_RDA_DATA1(n) ((uint32_t)(n&0xFF))
+/** CAN Receive Data 2 */
+#define CAN_RDA_DATA2(n) ((uint32_t)((n&0xFF)<<8))
+/** CAN Receive Data 3 */
+#define CAN_RDA_DATA3(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Receive Data 4 */
+#define CAN_RDA_DATA4(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Receive Data B Register
+ **********************************************************************/
+/** CAN Receive Data 5 */
+#define CAN_RDB_DATA5(n) ((uint32_t)(n&0xFF))
+/** CAN Receive Data 6 */
+#define CAN_RDB_DATA6(n) ((uint32_t)((n&0xFF)<<8))
+/** CAN Receive Data 7 */
+#define CAN_RDB_DATA7(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Receive Data 8 */
+#define CAN_RDB_DATA8(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Transmit Frame Information Register
+ **********************************************************************/
+/** CAN Priority */
+#define CAN_TFI_PRIO(n) ((uint32_t)(n&0xFF))
+/** CAN Data Length Code */
+#define CAN_TFI_DLC(n) ((uint32_t)((n&0xF)<<16))
+/** CAN Remote Frame Transmission */
+#define CAN_TFI_RTR ((uint32_t)(1<<30))
+/** CAN control 11-bit or 29-bit Identifier */
+#define CAN_TFI_FF ((uint32_t)(1<<31))
+
+/*********************************************************************//**
+ * Macro defines for CAN Transmit Identifier Register
+ **********************************************************************/
+/** CAN 11-bit Identifier */
+#define CAN_TID_ID11(n) ((uint32_t)(n&0x7FF))
+/** CAN 11-bit Identifier */
+#define CAN_TID_ID29(n) ((uint32_t)(n&0x1FFFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for CAN Transmit Data A Register
+ **********************************************************************/
+/** CAN Transmit Data 1 */
+#define CAN_TDA_DATA1(n) ((uint32_t)(n&0xFF))
+/** CAN Transmit Data 2 */
+#define CAN_TDA_DATA2(n) ((uint32_t)((n&0xFF)<<8))
+/** CAN Transmit Data 3 */
+#define CAN_TDA_DATA3(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Transmit Data 4 */
+#define CAN_TDA_DATA4(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Transmit Data B Register
+ **********************************************************************/
+/** CAN Transmit Data 5 */
+#define CAN_TDA_DATA5(n) ((uint32_t)(n&0xFF))
+/** CAN Transmit Data 6 */
+#define CAN_TDA_DATA6(n) ((uint32_t)((n&0xFF)<<8))
+/** CAN Transmit Data 7 */
+#define CAN_TDA_DATA7(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Transmit Data 8 */
+#define CAN_TDA_DATA8(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Sleep Clear Register
+ **********************************************************************/
+/** CAN1 Sleep mode */
+#define CAN1SLEEPCLR ((uint32_t)(1<<1))
+/** CAN2 Sleep Mode */
+#define CAN2SLEEPCLR ((uint32_t)(1<<2))
+
+/*********************************************************************//**
+ * Macro defines for CAN Wake up Flags Register
+ **********************************************************************/
+/** CAN1 Sleep mode */
+#define CAN_WAKEFLAGES_CAN1WAKE ((uint32_t)(1<<1))
+/** CAN2 Sleep Mode */
+#define CAN_WAKEFLAGES_CAN2WAKE ((uint32_t)(1<<2))
+
+/*********************************************************************//**
+ * Macro defines for Central transmit Status Register
+ **********************************************************************/
+/** CAN Transmit 1 */
+#define CAN_TSR_TS1 ((uint32_t)(1))
+/** CAN Transmit 2 */
+#define CAN_TSR_TS2 ((uint32_t)(1<<1))
+/** CAN Transmit Buffer Status 1 */
+#define CAN_TSR_TBS1 ((uint32_t)(1<<8))
+/** CAN Transmit Buffer Status 2 */
+#define CAN_TSR_TBS2 ((uint32_t)(1<<9))
+/** CAN Transmission Complete Status 1 */
+#define CAN_TSR_TCS1 ((uint32_t)(1<<16))
+/** CAN Transmission Complete Status 2 */
+#define CAN_TSR_TCS2 ((uint32_t)(1<<17))
+
+/*********************************************************************//**
+ * Macro defines for Central Receive Status Register
+ **********************************************************************/
+/** CAN Receive Status 1 */
+#define CAN_RSR_RS1 ((uint32_t)(1))
+/** CAN Receive Status 1 */
+#define CAN_RSR_RS2 ((uint32_t)(1<<1))
+/** CAN Receive Buffer Status 1*/
+#define CAN_RSR_RB1 ((uint32_t)(1<<8))
+/** CAN Receive Buffer Status 2*/
+#define CAN_RSR_RB2 ((uint32_t)(1<<9))
+/** CAN Data Overrun Status 1 */
+#define CAN_RSR_DOS1 ((uint32_t)(1<<16))
+/** CAN Data Overrun Status 1 */
+#define CAN_RSR_DOS2 ((uint32_t)(1<<17))
+
+/*********************************************************************//**
+ * Macro defines for Central Miscellaneous Status Register
+ **********************************************************************/
+/** Same CAN Error Status in CAN1GSR */
+#define CAN_MSR_E1 ((uint32_t)(1))
+/** Same CAN Error Status in CAN2GSR */
+#define CAN_MSR_E2 ((uint32_t)(1<<1))
+/** Same CAN Bus Status in CAN1GSR */
+#define CAN_MSR_BS1 ((uint32_t)(1<<8))
+/** Same CAN Bus Status in CAN2GSR */
+#define CAN_MSR_BS2 ((uint32_t)(1<<9))
+
+/*********************************************************************//**
+ * Macro defines for Acceptance Filter Mode Register
+ **********************************************************************/
+/** CAN Acceptance Filter Off mode */
+#define CAN_AFMR_AccOff ((uint32_t)(1))
+/** CAN Acceptance File Bypass mode */
+#define CAN_AFMR_AccBP ((uint32_t)(1<<1))
+/** FullCAN Mode Enhancements */
+#define CAN_AFMR_eFCAN ((uint32_t)(1<<2))
+
+/*********************************************************************//**
+ * Macro defines for Standard Frame Individual Start Address Register
+ **********************************************************************/
+/** The start address of the table of individual Standard Identifier */
+#define CAN_STT_sa(n) ((uint32_t)((n&1FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for Standard Frame Group Start Address Register
+ **********************************************************************/
+/** The start address of the table of grouped Standard Identifier */
+#define CAN_SFF_GRP_sa(n) ((uint32_t)((n&3FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for Extended Frame Start Address Register
+ **********************************************************************/
+/** The start address of the table of individual Extended Identifier */
+#define CAN_EFF_sa(n) ((uint32_t)((n&1FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for Extended Frame Group Start Address Register
+ **********************************************************************/
+/** The start address of the table of grouped Extended Identifier */
+#define CAN_Eff_GRP_sa(n) ((uint32_t)((n&3FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for End Of AF Table Register
+ **********************************************************************/
+/** The End of Table of AF LookUp Table */
+#define CAN_EndofTable(n) ((uint32_t)((n&3FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for LUT Error Address Register
+ **********************************************************************/
+/** CAN Look-Up Table Error Address */
+#define CAN_LUTerrAd(n) ((uint32_t)((n&1FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for LUT Error Register
+ **********************************************************************/
+/** CAN Look-Up Table Error */
+#define CAN_LUTerr ((uint32_t)(1))
+
+/*********************************************************************//**
+ * Macro defines for Global FullCANInterrupt Enable Register
+ **********************************************************************/
+/** Global FullCANInterrupt Enable */
+#define CAN_FCANIE ((uint32_t)(1))
+
+/*********************************************************************//**
+ * Macro defines for FullCAN Interrupt and Capture Register 0
+ **********************************************************************/
+/** FullCAN Interrupt and Capture (0-31)*/
+#define CAN_FCANIC0_IntPnd(n) ((uint32_t)(1<<n))
+
+/*********************************************************************//**
+ * Macro defines for FullCAN Interrupt and Capture Register 1
+ **********************************************************************/
+/** FullCAN Interrupt and Capture (0-31)*/
+#define CAN_FCANIC1_IntPnd(n) ((uint32_t)(1<<(n-32)))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid CAN peripheral or not */
+#define PARAM_CANx(x) ((((uint32_t*)x)==((uint32_t *)LPC_CAN1)) \
+||(((uint32_t*)x)==((uint32_t *)LPC_CAN2)))
+
+/* Macro to determine if it is valid CANAF or not*/
+#define PARAM_CANAFx(x) (((uint32_t*)x)== ((uint32_t*)LPC_CANAF))
+
+/* Macro to determine if it is valid CANAF RAM or not*/
+#define PARAM_CANAFRAMx(x) (((uint32_t*)x)== (uint32_t*)LPC_CANAF_RAM)
+
+/* Macro to determine if it is valid CANCR or not*/
+#define PARAM_CANCRx(x) (((uint32_t*)x)==((uint32_t*)LPC_CANCR))
+
+/** Macro to check Data to send valid */
+#define PARAM_I2S_DATA(data) ((data>=0)&&(data <= 0xFFFFFFFF))
+
+/** Macro to check frequency value */
+#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
+
+/** Macro to check Frame Identifier */
+#define PARAM_ID_11(n) ((n>>11)==0) /*-- 11 bit --*/
+#define PARAM_ID_29(n) ((n>>29)==0) /*-- 29 bit --*/
+
+/** Macro to check DLC value */
+#define PARAM_DLC(n) ((n>>4)==0) /*-- 4 bit --*/
+/** Macro to check ID format type */
+#define PARAM_ID_FORMAT(n) ((n==STD_ID_FORMAT)||(n==EXT_ID_FORMAT))
+
+/** Macro to check Group identifier */
+#define PARAM_GRP_ID(x, y) ((x<=y))
+
+/** Macro to check Frame type */
+#define PARAM_FRAME_TYPE(n) ((n==DATA_FRAME)||(n==REMOTE_FRAME))
+
+/** Macro to check Control/Central Status type parameter */
+#define PARAM_CTRL_STS_TYPE(n) ((n==CANCTRL_GLOBAL_STS)||(n==CANCTRL_INT_CAP) \
+||(n==CANCTRL_ERR_WRN)||(n==CANCTRL_STS))
+
+/** Macro to check CR status type */
+#define PARAM_CR_STS_TYPE(n) ((n==CANCR_TX_STS)||(n==CANCR_RX_STS) \
+||(n==CANCR_MS))
+/** Macro to check AF Mode type parameter */
+#define PARAM_AFMODE_TYPE(n) ((n==CAN_Normal)||(n==CAN_AccOff) \
+||(n==CAN_AccBP)||(n==CAN_eFCAN))
+
+/** Macro to check Operation Mode */
+#define PARAM_MODE_TYPE(n) ((n==CAN_OPERATING_MODE)||(n==CAN_RESET_MODE) \
+||(n==CAN_LISTENONLY_MODE)||(n==CAN_SELFTEST_MODE) \
+||(n==CAN_TXPRIORITY_MODE)||(n==CAN_SLEEP_MODE) \
+||(n==CAN_RXPOLARITY_MODE)||(n==CAN_TEST_MODE))
+
+/** Macro define for struct AF_Section parameter */
+#define PARAM_CTRL(n) ((n==CAN1_CTRL)|(n==CAN2_CTRL))
+
+/** Macro define for struct AF_Section parameter */
+#define PARAM_MSG_DISABLE(n) ((n==MSG_ENABLE)|(n==MSG_DISABLE))
+
+/**Macro to check Interrupt Type parameter */
+#define PARAM_INT_EN_TYPE(n) ((n==CANINT_RIE)||(n==CANINT_TIE1) \
+||(n==CANINT_EIE)||(n==CANINT_DOIE) \
+||(n==CANINT_WUIE)||(n==CANINT_EPIE) \
+||(n==CANINT_ALIE)||(n==CANINT_BEIE) \
+||(n==CANINT_IDIE)||(n==CANINT_TIE2) \
+||(n==CANINT_TIE3)||(n==CANINT_FCE))
+
+/** Macro to check AFLUT Entry type */
+#define PARAM_AFLUT_ENTRY_TYPE(n) ((n==FULLCAN_ENTRY)||(n==EXPLICIT_STANDARD_ENTRY)\
+||(n==GROUP_STANDARD_ENTRY)||(n==EXPLICIT_EXTEND_ENTRY) \
+||(n==GROUP_EXTEND_ENTRY))
+
+/** Macro to check position */
+#define PARAM_POSITION(n) ((n>=0)&&(n<512))
+
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup CAN_Public_Types CAN Public Types
+ * @{
+ */
+
+/** CAN configuration structure */
+/***********************************************************************
+ * CAN device configuration commands (IOCTL commands and arguments)
+ **********************************************************************/
+/**
+ * @brief CAN ID format definition
+ */
+typedef enum {
+ STD_ID_FORMAT = 0, /**< Use standard ID format (11 bit ID) */
+ EXT_ID_FORMAT = 1 /**< Use extended ID format (29 bit ID) */
+} CAN_ID_FORMAT_Type;
+
+/**
+ * @brief AFLUT Entry type definition
+ */
+typedef enum {
+ FULLCAN_ENTRY = 0,
+ EXPLICIT_STANDARD_ENTRY,
+ GROUP_STANDARD_ENTRY,
+ EXPLICIT_EXTEND_ENTRY,
+ GROUP_EXTEND_ENTRY,
+} AFLUT_ENTRY_Type;
+
+/**
+ * @brief Symbolic names for type of CAN message
+ */
+typedef enum {
+ DATA_FRAME = 0, /**< Data frame */
+ REMOTE_FRAME = 1 /**< Remote frame */
+} CAN_FRAME_Type;
+
+/**
+ * @brief CAN Control status definition
+ */
+typedef enum {
+ CANCTRL_GLOBAL_STS = 0, /**< CAN Global Status */
+ CANCTRL_INT_CAP, /**< CAN Interrupt and Capture */
+ CANCTRL_ERR_WRN, /**< CAN Error Warning Limit */
+ CANCTRL_STS /**< CAN Control Status */
+} CAN_CTRL_STS_Type;
+
+/**
+ * @brief Central CAN status type definition
+ */
+typedef enum {
+ CANCR_TX_STS = 0, /**< Central CAN Tx Status */
+ CANCR_RX_STS, /**< Central CAN Rx Status */
+ CANCR_MS /**< Central CAN Miscellaneous Status */
+} CAN_CR_STS_Type;
+
+/**
+ * @brief FullCAN Interrupt Capture type definition
+ */
+typedef enum{
+ FULLCAN_IC0, /**< FullCAN Interrupt and Capture 0 */
+ FULLCAN_IC1 /**< FullCAN Interrupt and Capture 1 */
+}FullCAN_IC_Type;
+
+/**
+ * @brief CAN interrupt enable type definition
+ */
+typedef enum {
+ CANINT_RIE = 0, /**< CAN Receiver Interrupt Enable */
+ CANINT_TIE1, /**< CAN Transmit Interrupt Enable */
+ CANINT_EIE, /**< CAN Error Warning Interrupt Enable */
+ CANINT_DOIE, /**< CAN Data Overrun Interrupt Enable */
+ CANINT_WUIE, /**< CAN Wake-Up Interrupt Enable */
+ CANINT_EPIE, /**< CAN Error Passive Interrupt Enable */
+ CANINT_ALIE, /**< CAN Arbitration Lost Interrupt Enable */
+ CANINT_BEIE, /**< CAN Bus Error Inter rupt Enable */
+ CANINT_IDIE, /**< CAN ID Ready Interrupt Enable */
+ CANINT_TIE2, /**< CAN Transmit Interrupt Enable for Buffer2 */
+ CANINT_TIE3, /**< CAN Transmit Interrupt Enable for Buffer3 */
+ CANINT_FCE /**< FullCAN Interrupt Enable */
+} CAN_INT_EN_Type;
+
+/**
+ * @brief Acceptance Filter Mode type definition
+ */
+typedef enum {
+ CAN_Normal = 0, /**< Normal Mode */
+ CAN_AccOff, /**< Acceptance Filter Off Mode */
+ CAN_AccBP, /**< Acceptance Fileter Bypass Mode */
+ CAN_eFCAN /**< FullCAN Mode Enhancement */
+} CAN_AFMODE_Type;
+
+/**
+ * @brief CAN Mode Type definition
+ */
+typedef enum {
+ CAN_OPERATING_MODE = 0, /**< Operating Mode */
+ CAN_RESET_MODE, /**< Reset Mode */
+ CAN_LISTENONLY_MODE, /**< Listen Only Mode */
+ CAN_SELFTEST_MODE, /**< Seft Test Mode */
+ CAN_TXPRIORITY_MODE, /**< Transmit Priority Mode */
+ CAN_SLEEP_MODE, /**< Sleep Mode */
+ CAN_RXPOLARITY_MODE, /**< Receive Polarity Mode */
+ CAN_TEST_MODE /**< Test Mode */
+} CAN_MODE_Type;
+
+/**
+ * @brief Error values that functions can return
+ */
+typedef enum {
+ CAN_OK = 1, /**< No error */
+ CAN_OBJECTS_FULL_ERROR, /**< No more rx or tx objects available */
+ CAN_FULL_OBJ_NOT_RCV, /**< Full CAN object not received */
+ CAN_NO_RECEIVE_DATA, /**< No have receive data available */
+ CAN_AF_ENTRY_ERROR, /**< Entry load in AFLUT is unvalid */
+ CAN_CONFLICT_ID_ERROR, /**< Conflict ID occur */
+ CAN_ENTRY_NOT_EXIT_ERROR /**< Entry remove outo AFLUT is not exit */
+} CAN_ERROR;
+
+/**
+ * @brief Pin Configuration structure
+ */
+typedef struct {
+ uint8_t RD; /**< Serial Inputs, from CAN transceivers, should be:
+ ** For CAN1:
+ - CAN_RD1_P0_0: RD pin is on P0.0
+ - CAN_RD1_P0_21 : RD pin is on P0.21
+ ** For CAN2:
+ - CAN_RD2_P0_4: RD pin is on P0.4
+ - CAN_RD2_P2_7: RD pin is on P2.7
+ */
+ uint8_t TD; /**< Serial Outputs, To CAN transceivers, should be:
+ ** For CAN1:
+ - CAN_TD1_P0_1: TD pin is on P0.1
+ - CAN_TD1_P0_22: TD pin is on P0.22
+ ** For CAN2:
+ - CAN_TD2_P0_5: TD pin is on P0.5
+ - CAN_TD2_P2_8: TD pin is on P2.8
+ */
+} CAN_PinCFG_Type;
+
+/**
+ * @brief CAN message object structure
+ */
+typedef struct {
+ uint32_t id; /**< 29 bit identifier, it depend on "format" value
+ - if format = STD_ID_FORMAT, id should be 11 bit identifier
+ - if format = EXT_ID_FORMAT, id should be 29 bit identifier
+ */
+ uint8_t dataA[4]; /**< Data field A */
+ uint8_t dataB[4]; /**< Data field B */
+ uint8_t len; /**< Length of data field in bytes, should be:
+ - 0000b-0111b: 0-7 bytes
+ - 1xxxb: 8 bytes
+ */
+ uint8_t format; /**< Identifier Format, should be:
+ - STD_ID_FORMAT: Standard ID - 11 bit format
+ - EXT_ID_FORMAT: Extended ID - 29 bit format
+ */
+ uint8_t type; /**< Remote Frame transmission, should be:
+ - DATA_FRAME: the number of data bytes called out by the DLC
+ field are send from the CANxTDA and CANxTDB registers
+ - REMOTE_FRAME: Remote Frame is sent
+ */
+} CAN_MSG_Type;
+
+/**
+ * @brief FullCAN Entry structure
+ */
+typedef struct {
+ uint8_t controller; /**< CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t disable; /**< Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint16_t id_11; /**< Standard ID, should be 11-bit value */
+} FullCAN_Entry;
+
+/**
+ * @brief Standard ID Frame Format Entry structure
+ */
+typedef struct {
+ uint8_t controller; /**< CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t disable; /**< Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint16_t id_11; /**< Standard ID, should be 11-bit value */
+} SFF_Entry;
+
+/**
+ * @brief Group of Standard ID Frame Format Entry structure
+ */
+typedef struct {
+ uint8_t controller1; /**< First CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t disable1; /**< First Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0)
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint16_t lowerID; /**< ID lower bound, should be 11-bit value */
+ uint8_t controller2; /**< Second CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t disable2; /**< Second Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint16_t upperID; /**< ID upper bound, should be 11-bit value and
+ equal or greater than lowerID
+ */
+} SFF_GPR_Entry;
+
+/**
+ * @brief Extended ID Frame Format Entry structure
+ */
+typedef struct {
+ uint8_t controller; /**< CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint32_t ID_29; /**< Extend ID, shoud be 29-bit value */
+} EFF_Entry;
+
+
+/**
+ * @brief Group of Extended ID Frame Format Entry structure
+ */
+typedef struct {
+ uint8_t controller1; /**< First CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t controller2; /**< Second Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0(default)
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint32_t lowerEID; /**< Extended ID lower bound, should be 29-bit value */
+ uint32_t upperEID; /**< Extended ID upper bound, should be 29-bit value */
+} EFF_GPR_Entry;
+
+
+/**
+ * @brief Acceptance Filter Section Table structure
+ */
+typedef struct {
+ FullCAN_Entry* FullCAN_Sec; /**< The pointer point to FullCAN_Entry */
+ uint8_t FC_NumEntry; /**< FullCAN Entry Number */
+ SFF_Entry* SFF_Sec; /**< The pointer point to SFF_Entry */
+ uint8_t SFF_NumEntry; /**< Standard ID Entry Number */
+ SFF_GPR_Entry* SFF_GPR_Sec; /**< The pointer point to SFF_GPR_Entry */
+ uint8_t SFF_GPR_NumEntry; /**< Group Standard ID Entry Number */
+ EFF_Entry* EFF_Sec; /**< The pointer point to EFF_Entry */
+ uint8_t EFF_NumEntry; /**< Extended ID Entry Number */
+ EFF_GPR_Entry* EFF_GPR_Sec; /**< The pointer point to EFF_GPR_Entry */
+ uint8_t EFF_GPR_NumEntry; /**< Group Extended ID Entry Number */
+} AF_SectionDef;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CAN_Public_Functions CAN Public Functions
+ * @{
+ */
+
+/* Init/DeInit CAN peripheral -----------*/
+void CAN_Init(LPC_CAN_TypeDef *CANx, uint32_t baudrate);
+void CAN_DeInit(LPC_CAN_TypeDef *CANx);
+
+/* CAN messages functions ---------------*/
+Status CAN_SendMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg);
+Status CAN_ReceiveMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg);
+CAN_ERROR FCAN_ReadObj(LPC_CANAF_TypeDef* CANAFx, CAN_MSG_Type *CAN_Msg);
+
+/* CAN configure functions ---------------*/
+void CAN_ModeConfig(LPC_CAN_TypeDef* CANx, CAN_MODE_Type mode,
+ FunctionalState NewState);
+void CAN_SetAFMode(LPC_CANAF_TypeDef* CANAFx, CAN_AFMODE_Type AFmode);
+void CAN_SetCommand(LPC_CAN_TypeDef* CANx, uint32_t CMRType);
+
+/* AFLUT functions ---------------------- */
+CAN_ERROR CAN_SetupAFLUT(LPC_CANAF_TypeDef* CANAFx, AF_SectionDef* AFSection);
+CAN_ERROR CAN_LoadFullCANEntry(LPC_CAN_TypeDef* CANx, uint16_t ID);
+CAN_ERROR CAN_LoadExplicitEntry(LPC_CAN_TypeDef* CANx, uint32_t ID,
+ CAN_ID_FORMAT_Type format);
+CAN_ERROR CAN_LoadGroupEntry(LPC_CAN_TypeDef* CANx, uint32_t lowerID,
+ uint32_t upperID, CAN_ID_FORMAT_Type format);
+CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position);
+
+/* CAN interrupt functions -----------------*/
+void CAN_IRQCmd(LPC_CAN_TypeDef* CANx, CAN_INT_EN_Type arg, FunctionalState NewState);
+uint32_t CAN_IntGetStatus(LPC_CAN_TypeDef* CANx);
+
+/* CAN get status functions ----------------*/
+IntStatus CAN_FullCANIntGetStatus (LPC_CANAF_TypeDef* CANAFx);
+uint32_t CAN_FullCANPendGetStatus (LPC_CANAF_TypeDef* CANAFx, FullCAN_IC_Type type);
+uint32_t CAN_GetCTRLStatus(LPC_CAN_TypeDef* CANx, CAN_CTRL_STS_Type arg);
+uint32_t CAN_GetCRStatus(LPC_CANCR_TypeDef* CANCRx, CAN_CR_STS_Type arg);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_CAN_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_clkpwr.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_clkpwr.h new file mode 100644 index 0000000..b8876e2 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_clkpwr.h @@ -0,0 +1,394 @@ +/***********************************************************************//**
+ * @file lpc17xx_clkpwr.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for Clock and Power Control firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CLKPWR CLKPWR
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_CLKPWR_H_
+#define LPC17XX_CLKPWR_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
+ * @{
+ */
+
+/**********************************************************************
+ * Peripheral Clock Selection Definitions
+ **********************************************************************/
+/** Peripheral clock divider bit position for WDT */
+#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
+/** Peripheral clock divider bit position for TIMER0 */
+#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
+/** Peripheral clock divider bit position for TIMER1 */
+#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
+/** Peripheral clock divider bit position for UART0 */
+#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
+/** Peripheral clock divider bit position for UART1 */
+#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
+/** Peripheral clock divider bit position for PWM1 */
+#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
+/** Peripheral clock divider bit position for I2C0 */
+#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
+/** Peripheral clock divider bit position for SPI */
+#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
+/** Peripheral clock divider bit position for SSP1 */
+#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
+/** Peripheral clock divider bit position for DAC */
+#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
+/** Peripheral clock divider bit position for ADC */
+#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
+/** Peripheral clock divider bit position for CAN1 */
+#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
+/** Peripheral clock divider bit position for CAN2 */
+#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
+/** Peripheral clock divider bit position for ACF */
+#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
+/** Peripheral clock divider bit position for QEI */
+#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
+/** Peripheral clock divider bit position for PCB */
+#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
+/** Peripheral clock divider bit position for I2C1 */
+#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
+/** Peripheral clock divider bit position for SSP0 */
+#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
+/** Peripheral clock divider bit position for TIMER2 */
+#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
+/** Peripheral clock divider bit position for TIMER3 */
+#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
+/** Peripheral clock divider bit position for UART2 */
+#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
+/** Peripheral clock divider bit position for UART3 */
+#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
+/** Peripheral clock divider bit position for I2C2 */
+#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
+/** Peripheral clock divider bit position for I2S */
+#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
+/** Peripheral clock divider bit position for RIT */
+#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
+/** Peripheral clock divider bit position for SYSCON */
+#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
+/** Peripheral clock divider bit position for MC */
+#define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
+
+/** Macro for Peripheral Clock Selection register bit values
+ * Note: When CCLK_DIV_8, Peripheral’s clock is selected to
+ * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
+ * when ’11’selects PCLK_xyz = CCLK/6 */
+/* Peripheral clock divider is set to 4 from CCLK */
+#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
+/** Peripheral clock divider is the same with CCLK */
+#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
+/** Peripheral clock divider is set to 2 from CCLK */
+#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
+
+
+/********************************************************************
+* Power Control for Peripherals Definitions
+**********************************************************************/
+/** Timer/Counter 0 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
+/* Timer/Counter 1 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
+/** UART0 power/clock control bit */
+#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
+/** UART1 power/clock control bit */
+#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
+/** PWM1 power/clock control bit */
+#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
+/** The I2C0 interface power/clock control bit */
+#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
+/** The SPI interface power/clock control bit */
+#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
+/** The RTC power/clock control bit */
+#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
+/** The SSP1 interface power/clock control bit */
+#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
+/** A/D converter 0 (ADC0) power/clock control bit */
+#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
+/** CAN Controller 1 power/clock control bit */
+#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
+/** CAN Controller 2 power/clock control bit */
+#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
+/** GPIO power/clock control bit */
+#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
+/** Repetitive Interrupt Timer power/clock control bit */
+#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
+/** Motor Control PWM */
+#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
+/** Quadrature Encoder Interface power/clock control bit */
+#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
+/** The I2C1 interface power/clock control bit */
+#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
+/** The SSP0 interface power/clock control bit */
+#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
+/** Timer 2 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
+/** Timer 3 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
+/** UART 2 power/clock control bit */
+#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
+/** UART 3 power/clock control bit */
+#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
+/** I2C interface 2 power/clock control bit */
+#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
+/** I2S interface power/clock control bit*/
+#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
+/** GP DMA function power/clock control bit*/
+#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
+/** Ethernet block power/clock control bit*/
+#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
+/** USB interface power/clock control bit*/
+#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
+
+
+/**
+ * @}
+ */
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Clock Source Select Register
+ **********************************************************************/
+/** Internal RC oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
+/** Main oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
+/** RTC oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
+/** Clock source selection bit mask */
+#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for Clock Output Configuration Register
+ **********************************************************************/
+/* Clock Output Configuration register definition */
+/** Selects the CPU clock as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
+/** Selects the main oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
+/** Selects the Internal RC oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
+/** Selects the USB clock as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
+/** Selects the RTC oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
+/** Integer value to divide the output clock by, minus one */
+#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
+/** CLKOUT enable control */
+#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
+/** CLKOUT activity indication */
+#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
+/** Clock source selection bit mask */
+#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Control Register
+ **********************************************************************/
+/** PLL 0 control enable */
+#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
+/** PLL 0 control connect */
+#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
+/** PLL 0 control bit mask */
+#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Configuration Register
+ **********************************************************************/
+/** PLL 0 Configuration MSEL field */
+#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
+/** PLL 0 Configuration NSEL field */
+#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
+/** PLL 0 Configuration bit mask */
+#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
+
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Status Register
+ **********************************************************************/
+/** PLL 0 MSEL value */
+#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
+/** PLL NSEL get value */
+#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
+/** PLL status enable bit */
+#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
+/** PLL status Connect bit */
+#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
+/** PLL status lock */
+#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Feed Register
+ **********************************************************************/
+/** PLL0 Feed bit mask */
+#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Control Register
+ **********************************************************************/
+/** USB PLL control enable */
+#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
+/** USB PLL control connect */
+#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
+/** USB PLL control bit mask */
+#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Configuration Register
+ **********************************************************************/
+/** USB PLL MSEL set value */
+#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
+/** USB PLL PSEL set value */
+#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
+/** USB PLL configuration bit mask */
+#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Status Register
+ **********************************************************************/
+/** USB PLL MSEL get value */
+#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
+/** USB PLL PSEL get value */
+#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
+/** USB PLL status enable bit */
+#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
+/** USB PLL status Connect bit */
+#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
+/** USB PLL status lock */
+#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Feed Register
+ **********************************************************************/
+/** PLL1 Feed bit mask */
+#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for CPU Clock Configuration Register
+ **********************************************************************/
+/** CPU Clock configuration bit mask */
+#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for USB Clock Configuration Register
+ **********************************************************************/
+/** USB Clock Configuration bit mask */
+#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for IRC Trim Register
+ **********************************************************************/
+/** IRC Trim bit mask */
+#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for Peripheral Clock Selection Register 0 and 1
+ **********************************************************************/
+/** Peripheral Clock Selection 0 mask bit */
+#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
+/** Peripheral Clock Selection 1 mask bit */
+#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
+/** Macro to set peripheral clock of each type
+ * p: position of two bits that hold divider of peripheral clock
+ * n: value of divider of peripheral clock to be set */
+#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
+/** Macro to mask peripheral clock of each type */
+#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
+/** Macro to get peripheral clock of each type */
+#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
+
+/*********************************************************************//**
+ * Macro defines for Power Mode Control Register
+ **********************************************************************/
+/** Power mode control bit 0 */
+#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
+/** Power mode control bit 1 */
+#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
+/** Brown-Out Reduced Power Mode */
+#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
+/** Brown-Out Global Disable */
+#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
+/** Brown Out Reset Disable */
+#define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
+/** Sleep Mode entry flag */
+#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
+/** Deep Sleep entry flag */
+#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
+/** Power-down entry flag */
+#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
+/** Deep Power-down entry flag */
+#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
+
+/*********************************************************************//**
+ * Macro defines for Power Control for Peripheral Register
+ **********************************************************************/
+/** Power Control for Peripherals bit mask */
+#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
+ * @{
+ */
+
+void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
+uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
+uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
+void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
+void CLKPWR_Sleep(void);
+void CLKPWR_DeepSleep(void);
+void CLKPWR_PowerDown(void);
+void CLKPWR_DeepPowerDown(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_CLKPWR_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_dac.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_dac.h new file mode 100644 index 0000000..1e382b7 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_dac.h @@ -0,0 +1,142 @@ +/***********************************************************************//**
+ * @file lpc17xx_dac.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for DAC firmware library on LPC17xx
+ * @version 3.0
+ * @date 18. June. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup DAC DAC
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_DAC_H_
+#define LPC17XX_DAC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+
+/** After the selected settling time after this field is written with a
+new VALUE, the voltage on the AOUT pin (with respect to VSSA)
+is VALUE/1024 × VREF */
+#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6))
+/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
+ * and the maximum current is 700 microAmpere
+ * If this bit = 1: The settling time of the DAC is 2.5 microsecond
+ * and the maximum current is 350 microAmpere */
+#define DAC_BIAS_EN ((uint32_t)(1<<16))
+/** Value to reload interrupt DMA counter */
+#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff))
+
+/** DCAR double buffering */
+#define DAC_DBLBUF_ENA ((uint32_t)(1<<1))
+/** DCAR Time out count enable */
+#define DAC_CNT_ENA ((uint32_t)(1<<2))
+/** DCAR DMA access */
+#define DAC_DMA_ENA ((uint32_t)(1<<3))
+/** DCAR DACCTRL mask bit */
+#define DAC_DACCTRL_MASK ((uint32_t)(0x0F))
+
+/** Macro to determine if it is valid DAC peripheral */
+#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC))
+
+/** Macro to check DAC current optional parameter */
+#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\
+||(OPTION == DAC_MAX_CURRENT_350uA))
+/**
+ * @}
+ */
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup DAC_Public_Types DAC Public Types
+ * @{
+ */
+
+/**
+ * @brief Current option in DAC configuration option */
+typedef enum
+{
+ DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max,
+ and the maximum current is 700 uA */
+ DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us
+ and the maximum current is 350 uA */
+} DAC_CURRENT_OPT;
+
+/**
+ * @brief Configuration for DAC converter control register */
+typedef struct
+{
+
+ uint8_t DBLBUF_ENA; /**<
+ -0: Disable DACR double buffering
+ -1: when bit CNT_ENA, enable DACR double buffering feature
+ */
+ uint8_t CNT_ENA; /*!<
+ -0: Time out counter is disable
+ -1: Time out conter is enable
+ */
+ uint8_t DMA_ENA; /*!<
+ -0: DMA access is disable
+ -1: DMA burst request
+ */
+ uint8_t RESERVED;
+
+} DAC_CONVERTER_CFG_Type;
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup DAC_Public_Functions DAC Public Functions
+ * @{
+ */
+
+void DAC_Init(LPC_DAC_TypeDef *DACx);
+void DAC_UpdateValue (LPC_DAC_TypeDef *DACx, uint32_t dac_value);
+void DAC_SetBias (LPC_DAC_TypeDef *DACx,uint32_t bias);
+void DAC_ConfigDAConverterControl (LPC_DAC_TypeDef *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);
+void DAC_SetDMATimeOut(LPC_DAC_TypeDef *DACx,uint32_t time_out);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_DAC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_emac.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_emac.h new file mode 100644 index 0000000..5055049 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_emac.h @@ -0,0 +1,699 @@ +/***********************************************************************//**
+ * @file lpc17xx_emac.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for Ethernet MAC firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup EMAC EMAC
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_EMAC_H_
+#define LPC17XX_EMAC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MCB_LPC_1768
+//#define IAR_LPC_1768
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup EMAC_Public_Macros EMAC Public Macros
+ * @{
+ */
+
+
+/* EMAC PHY status type definitions */
+#define EMAC_PHY_STAT_LINK (0) /**< Link Status */
+#define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
+#define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
+
+/* EMAC PHY device Speed definitions */
+#define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
+#define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
+#define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
+#define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
+#define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
+
+/**
+ * @}
+ */
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup EMAC_Private_Macros EMAC Private Macros
+ * @{
+ */
+
+
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
+#define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
+#define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
+#define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
+#define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for MAC Configuration Register 1
+ **********************************************************************/
+#define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
+#define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
+#define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
+#define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
+#define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
+#define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
+#define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
+#define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
+#define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
+#define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
+#define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
+
+/*********************************************************************//**
+ * Macro defines for MAC Configuration Register 2
+ **********************************************************************/
+#define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
+#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
+#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
+#define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
+#define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
+#define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
+#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
+#define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
+#define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
+#define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
+#define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
+#define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
+#define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
+
+/*********************************************************************//**
+ * Macro defines for Back-to-Back Inter-Packet-Gap Register
+ **********************************************************************/
+/** Programmable field representing the nibble time offset of the minimum possible period
+ * between the end of any transmitted packet to the beginning of the next */
+#define EMAC_IPGT_BBIPG(n) (n&0x7F)
+/** Recommended value for Full Duplex of Programmable field representing the nibble time
+ * offset of the minimum possible period between the end of any transmitted packet to the
+ * beginning of the next */
+#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
+/** Recommended value for Half Duplex of Programmable field representing the nibble time
+ * offset of the minimum possible period between the end of any transmitted packet to the
+ * beginning of the next */
+#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
+
+/*********************************************************************//**
+ * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
+ **********************************************************************/
+/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
+#define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
+/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
+#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
+/** Programmable field representing the optional carrierSense window referenced in
+ * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
+#define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
+/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
+#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
+
+/*********************************************************************//**
+ * Macro defines for Collision Window/Retry Register
+ **********************************************************************/
+/** Programmable field specifying the number of retransmission attempts following a collision before
+ * aborting the packet due to excessive collisions */
+#define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
+/** Programmable field representing the slot time or collision window during which collisions occur
+ * in properly configured networks */
+#define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
+/** Default value for Collision Window / Retry register */
+#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
+
+/*********************************************************************//**
+ * Macro defines for Maximum Frame Register
+ **********************************************************************/
+/** Represents a maximum receive frame of 1536 octets */
+#define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
+
+/*********************************************************************//**
+ * Macro defines for PHY Support Register
+ **********************************************************************/
+#define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
+#define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
+
+/*********************************************************************//**
+ * Macro defines for Test Register
+ **********************************************************************/
+#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
+#define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
+#define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Configuration Register
+ **********************************************************************/
+#define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
+#define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
+#define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
+#define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
+#define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Command Register
+ **********************************************************************/
+#define EMAC_MCMD_READ 0x00000001 /**< MII Read */
+#define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
+
+#define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
+#define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Address Register
+ **********************************************************************/
+#define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
+#define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Write Data Register
+ **********************************************************************/
+#define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Read Data Register
+ **********************************************************************/
+#define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Indicators Register
+ **********************************************************************/
+#define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
+#define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
+#define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
+#define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
+
+/* Station Address 0 Register */
+/* Station Address 1 Register */
+/* Station Address 2 Register */
+
+
+/* Control register definitions --------------------------------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Command Register
+ **********************************************************************/
+#define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
+#define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
+#define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
+#define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
+#define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
+#define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
+#define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
+#define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
+#define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
+#define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
+
+/*********************************************************************//**
+ * Macro defines for Status Register
+ **********************************************************************/
+#define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
+#define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
+
+/*********************************************************************//**
+ * Macro defines for Transmit Status Vector 0 Register
+ **********************************************************************/
+#define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
+#define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
+#define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
+#define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
+#define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
+#define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
+#define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
+#define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
+#define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
+#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
+#define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
+#define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
+#define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
+#define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
+#define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
+#define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
+#define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
+
+/*********************************************************************//**
+ * Macro defines for Transmit Status Vector 1 Register
+ **********************************************************************/
+#define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
+#define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
+
+/*********************************************************************//**
+ * Macro defines for Receive Status Vector Register
+ **********************************************************************/
+#define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
+#define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
+#define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
+#define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
+#define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
+#define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
+#define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
+#define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
+#define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
+#define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
+#define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
+#define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
+#define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
+#define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
+#define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
+#define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
+
+/*********************************************************************//**
+ * Macro defines for Flow Control Counter Register
+ **********************************************************************/
+#define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
+#define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
+
+/*********************************************************************//**
+ * Macro defines for Flow Control Status Register
+ **********************************************************************/
+#define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
+
+
+/* Receive filter register definitions -------------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Receive Filter Control Register
+ **********************************************************************/
+#define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
+#define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
+#define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
+#define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
+#define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
+#define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
+#define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
+#define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
+
+/*********************************************************************//**
+ * Macro defines for Receive Filter WoL Status/Clear Registers
+ **********************************************************************/
+#define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
+#define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
+#define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
+#define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
+#define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
+#define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
+#define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
+#define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
+#define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
+
+
+/* Module control register definitions ---------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Interrupt Status/Enable/Clear/Set Registers
+ **********************************************************************/
+#define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
+#define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
+#define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
+#define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
+#define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
+#define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
+#define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
+#define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
+#define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
+#define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
+
+/*********************************************************************//**
+ * Macro defines for Power Down Register
+ **********************************************************************/
+#define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
+
+/* Descriptor and status formats ---------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for RX Descriptor Control Word
+ **********************************************************************/
+#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
+#define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
+
+/*********************************************************************//**
+ * Macro defines for RX Status Hash CRC Word
+ **********************************************************************/
+#define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
+#define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
+
+/*********************************************************************//**
+ * Macro defines for RX Status Information Word
+ **********************************************************************/
+#define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
+#define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
+#define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
+#define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
+#define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
+#define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
+#define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
+#define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
+#define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
+#define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
+#define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
+#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
+#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
+#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
+#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
+#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
+EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
+
+/*********************************************************************//**
+ * Macro defines for TX Descriptor Control Word
+ **********************************************************************/
+#define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
+#define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
+#define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
+#define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
+#define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
+#define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
+#define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
+
+/*********************************************************************//**
+ * Macro defines for TX Status Information Word
+ **********************************************************************/
+#define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
+#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
+#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
+#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
+#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
+#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
+#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
+#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
+
+#ifdef MCB_LPC_1768
+/* DP83848C PHY definition ------------------------------------------------------------ */
+
+/** PHY device reset time out definition */
+#define EMAC_PHY_RESP_TOUT 0x100000UL
+
+/* ENET Device Revision ID */
+#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
+
+/*********************************************************************//**
+ * Macro defines for DP83848C PHY Registers
+ **********************************************************************/
+#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
+#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
+#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
+#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
+#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
+#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
+#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
+#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
+#define EMAC_PHY_REG_LPNPA 0x08
+
+/*********************************************************************//**
+ * Macro defines for PHY Extended Registers
+ **********************************************************************/
+#define EMAC_PHY_REG_STS 0x10 /**< Status Register */
+#define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
+#define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
+#define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
+#define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
+#define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
+#define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
+#define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
+#define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
+#define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
+#define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
+#define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Control Register
+ **********************************************************************/
+#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
+#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
+#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
+#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
+#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
+#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
+#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
+#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Status Status Register
+ **********************************************************************/
+#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
+#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
+#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
+#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
+#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
+#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
+#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
+#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
+#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
+#define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
+
+/*********************************************************************//**
+ * Macro defines for PHY Status Register
+ **********************************************************************/
+#define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
+#define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
+#define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
+#define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
+#define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
+#define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
+#define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
+
+#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
+#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
+#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
+#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
+#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
+
+#define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
+#define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
+
+#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
+#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
+#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
+
+#elif defined(IAR_LPC_1768)
+/* KSZ8721BL PHY definition ------------------------------------------------------------ */
+/** PHY device reset time out definition */
+#define EMAC_PHY_RESP_TOUT 0x100000UL
+
+/* ENET Device Revision ID */
+#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
+
+/*********************************************************************//**
+ * Macro defines for KSZ8721BL PHY Registers
+ **********************************************************************/
+#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
+#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
+#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
+#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
+#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
+#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
+#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
+#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
+#define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
+#define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
+#define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
+#define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Control Register
+ **********************************************************************/
+#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
+#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
+#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
+#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
+#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
+#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
+#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
+#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
+#define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
+#define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Status Register
+ **********************************************************************/
+#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
+#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
+#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
+#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
+#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
+#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
+#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
+#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
+#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
+#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
+#define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
+#define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
+
+/*********************************************************************//**
+ * Macro defines for PHY Identifier
+ **********************************************************************/
+/* PHY Identifier 1 bitmap definitions */
+#define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
+
+/* PHY Identifier 2 bitmap definitions */
+#define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
+
+/*********************************************************************//**
+ * Macro defines for Auto-Negotiation Advertisement
+ **********************************************************************/
+#define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
+#define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
+#define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
+#define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
+#define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
+#define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
+#define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
+#define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
+#define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
+
+#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
+#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
+#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
+#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
+#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
+
+#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
+#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
+
+#define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
+#define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup EMAC_Public_Types EMAC Public Types
+ * @{
+ */
+
+/* Descriptor and status formats ---------------------------------------------- */
+
+/**
+ * @brief RX Descriptor structure type definition
+ */
+typedef struct {
+ uint32_t Packet; /**< Receive Packet Descriptor */
+ uint32_t Ctrl; /**< Receive Control Descriptor */
+} RX_Desc;
+
+/**
+ * @brief RX Status structure type definition
+ */
+typedef struct {
+ uint32_t Info; /**< Receive Information Status */
+ uint32_t HashCRC; /**< Receive Hash CRC Status */
+} RX_Stat;
+
+/**
+ * @brief TX Descriptor structure type definition
+ */
+typedef struct {
+ uint32_t Packet; /**< Transmit Packet Descriptor */
+ uint32_t Ctrl; /**< Transmit Control Descriptor */
+} TX_Desc;
+
+/**
+ * @brief TX Status structure type definition
+ */
+typedef struct {
+ uint32_t Info; /**< Transmit Information Status */
+} TX_Stat;
+
+
+/**
+ * @brief TX Data Buffer structure definition
+ */
+typedef struct {
+ uint32_t ulDataLen; /**< Data length */
+ uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
+} EMAC_PACKETBUF_Type;
+
+/**
+ * @brief EMAC configuration structure definition
+ */
+typedef struct {
+ uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
+ - EMAC_MODE_AUTO
+ - EMAC_MODE_10M_FULL
+ - EMAC_MODE_10M_HALF
+ - EMAC_MODE_100M_FULL
+ - EMAC_MODE_100M_HALF
+ */
+ uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
+ of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
+ */
+} EMAC_CFG_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup EMAC_Public_Functions EMAC Public Functions
+ * @{
+ */
+/* Init/DeInit EMAC peripheral */
+Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
+void EMAC_DeInit(void);
+
+/* PHY functions --------------*/
+int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
+int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
+int32_t EMAC_UpdatePHYStatus(void);
+
+/* Filter functions ----------*/
+void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
+void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
+
+/* EMAC Packet Buffer functions */
+void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
+void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
+
+/* EMAC Interrupt functions -------*/
+void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
+IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
+
+/* EMAC Index functions -----------*/
+Bool EMAC_CheckReceiveIndex(void);
+Bool EMAC_CheckTransmitIndex(void);
+void EMAC_UpdateRxConsumeIndex(void);
+void EMAC_UpdateTxProduceIndex(void);
+
+FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
+uint32_t EMAC_GetReceiveDataSize(void);
+FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_EMAC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_exti.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_exti.h new file mode 100644 index 0000000..91ebb87 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_exti.h @@ -0,0 +1,143 @@ +/***********************************************************************//**
+ * @file lpc17xx_exti.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for External interrupt firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup EXTI EXTI
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_EXTI_H_
+#define LPC17XX_EXTI_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+ * @{
+ */
+/*********************************************************************//**
+ * Macro defines for EXTI control register
+ **********************************************************************/
+#define EXTI_EINT0_BIT_MARK 0x01
+#define EXTI_EINT1_BIT_MARK 0x02
+#define EXTI_EINT2_BIT_MARK 0x04
+#define EXTI_EINT3_BIT_MARK 0x08
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup EXTI_Public_Types EXTI Public Types
+ * @{
+ */
+
+/**
+ * @brief EXTI external interrupt line option
+ */
+typedef enum
+{
+ EXTI_EINT0, /*!< External interrupt 0, P2.10 */
+ EXTI_EINT1, /*!< External interrupt 0, P2.11 */
+ EXTI_EINT2, /*!< External interrupt 0, P2.12 */
+ EXTI_EINT3 /*!< External interrupt 0, P2.13 */
+} EXTI_LINE_ENUM;
+
+/**
+ * @brief EXTI mode option
+ */
+typedef enum
+{
+ EXTI_MODE_LEVEL_SENSITIVE, /*!< Level sensitivity is selected */
+ EXTI_MODE_EDGE_SENSITIVE /*!< Edge sensitivity is selected */
+} EXTI_MODE_ENUM;
+
+/**
+ * @brief EXTI polarity option
+ */
+typedef enum
+{
+ EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE, /*!< Low active or falling edge sensitive
+ depending on pin mode */
+ EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE /*!< High active or rising edge sensitive
+ depending on pin mode */
+} EXTI_POLARITY_ENUM;
+
+/**
+ * @brief EXTI Initialize structure
+ */
+typedef struct
+{
+ EXTI_LINE_ENUM EXTI_Line; /*!<Select external interrupt pin (EINT0, EINT1, EINT 2, EINT3) */
+
+ EXTI_MODE_ENUM EXTI_Mode; /*!< Choose between Level-sensitivity or Edge sensitivity */
+
+ EXTI_POLARITY_ENUM EXTI_polarity; /*!< If EXTI mode is level-sensitive: this element use to select low or high active level
+ if EXTI mode is polarity-sensitive: this element use to select falling or rising edge */
+
+}EXTI_InitTypeDef;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup EXTI_Public_Functions EXTI Public Functions
+ * @{
+ */
+
+void EXTI_Init(void);
+void EXTI_DeInit(void);
+
+void EXTI_Config(EXTI_InitTypeDef *EXTICfg);
+void EXTI_SetMode(EXTI_LINE_ENUM EXTILine, EXTI_MODE_ENUM mode);
+void EXTI_SetPolarity(EXTI_LINE_ENUM EXTILine, EXTI_POLARITY_ENUM polarity);
+void EXTI_ClearEXTIFlag(EXTI_LINE_ENUM EXTILine);
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_EXTI_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_gpdma.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_gpdma.h new file mode 100644 index 0000000..f2053fc --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_gpdma.h @@ -0,0 +1,417 @@ +/***********************************************************************//**
+ * @file lpc17xx_gpdma.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for GPDMA firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup GPDMA GPDMA
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_GPDMA_H_
+#define LPC17XX_GPDMA_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
+ * @{
+ */
+
+/** DMA Connection number definitions */
+#define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */
+#define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */
+#define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */
+#define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */
+#define GPDMA_CONN_ADC ((4UL)) /**< ADC */
+#define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */
+#define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */
+#define GPDMA_CONN_DAC ((7UL)) /**< DAC */
+#define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */
+#define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */
+#define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */
+#define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */
+#define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */
+#define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */
+#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
+#define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */
+#define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */
+#define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */
+#define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */
+#define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */
+#define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */
+#define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */
+#define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */
+#define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */
+
+/** GPDMA Transfer type definitions */
+#define GPDMA_TRANSFERTYPE_M2M ((0UL)) /**< Memory to memory - DMA control */
+#define GPDMA_TRANSFERTYPE_M2P ((1UL)) /**< Memory to peripheral - DMA control */
+#define GPDMA_TRANSFERTYPE_P2M ((2UL)) /**< Peripheral to memory - DMA control */
+#define GPDMA_TRANSFERTYPE_P2P ((3UL)) /**< Source peripheral to destination peripheral - DMA control */
+
+/** Burst size in Source and Destination definitions */
+#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
+#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
+#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
+#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
+#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
+#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
+#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
+#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
+
+/** Width in Source transfer width and Destination transfer width definitions */
+#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
+#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
+#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
+
+/** DMA Request Select Mode definitions */
+#define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */
+#define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Status register
+ **********************************************************************/
+#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Terminal Count Request Status register
+ **********************************************************************/
+#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Terminal Count Request Clear register
+ **********************************************************************/
+#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Error Status register
+ **********************************************************************/
+#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Error Clear register
+ **********************************************************************/
+#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Raw Interrupt Terminal Count Status register
+ **********************************************************************/
+#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Raw Error Interrupt Status register
+ **********************************************************************/
+#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Enabled Channel register
+ **********************************************************************/
+#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Burst Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Single Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Last Burst Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Last Single Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Configuration register
+ **********************************************************************/
+#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
+#define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/
+#define GPDMA_DMACConfig_BITMASK ((0x03))
+
+/*********************************************************************//**
+ * Macro defines for DMA Synchronization register
+ **********************************************************************/
+#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSync_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Request Select register
+ **********************************************************************/
+#define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
+#define GPDMA_DMAReqSel_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Channel Linked List Item registers
+ **********************************************************************/
+/** DMA Channel Linked List Item registers bit mask*/
+#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
+
+/*********************************************************************//**
+ * Macro defines for DMA channel control registers
+ **********************************************************************/
+#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/
+#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/
+#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/
+#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/
+#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/
+#define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/
+#define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/
+#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/
+#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/
+#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/
+#define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */
+/** DMA channel control registers bit mask */
+#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Channel Configuration registers
+ **********************************************************************/
+#define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/
+#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/
+#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/
+#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/
+#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/
+#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/
+#define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/
+#define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/
+#define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/
+/** DMA Channel Configuration registers bit mask */
+#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macros check GPDMA channel */
+#define PARAM_GPDMA_CHANNEL(n) ((n>=0) && (n<=7))
+
+/* Macros check GPDMA connection type */
+#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
+|| (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
+|| (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \
+|| (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \
+|| (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
+|| (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
+|| (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
+|| (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
+|| (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
+|| (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
+|| (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
+|| (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
+
+/* Macros check GPDMA burst size type */
+#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
+|| (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
+|| (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
+|| (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
+
+/* Macros check GPDMA width type */
+#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
+|| (n==GPDMA_WIDTH_WORD))
+
+/* Macros check GPDMA status type */
+#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
+|| (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
+|| (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
+
+/* Macros check GPDMA transfer type */
+#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \
+||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P))
+
+/* Macros check GPDMA state clear type */
+#define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
+
+/* Macros check GPDMA request select type */
+#define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Types GPDMA Public Types
+ * @{
+ */
+
+/**
+ * @brief GPDMA Status enumeration
+ */
+typedef enum {
+ GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
+ GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
+ GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
+ GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
+ GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
+ GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
+} GPDMA_Status_Type;
+
+/**
+ * @brief GPDMA Interrupt clear status enumeration
+ */
+typedef enum{
+ GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
+ GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
+}GPDMA_StateClear_Type;
+
+/**
+ * @brief GPDMA Channel configuration structure type definition
+ */
+typedef struct {
+ uint32_t ChannelNum; /**< DMA channel number, should be in
+ range from 0 to 7.
+ Note: DMA channel 0 has the highest priority
+ and DMA channel 7 the lowest priority.
+ */
+ uint32_t TransferSize; /**< Length/Size of transfer */
+ uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
+ uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
+ uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
+ uint32_t TransferType; /**< Transfer Type, should be one of the following:
+ - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
+ - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
+ - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
+ - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
+ */
+ uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
+ following:
+ - GPDMA_CONN_SSP0_Tx: SSP0, Tx
+ - GPDMA_CONN_SSP0_Rx: SSP0, Rx
+ - GPDMA_CONN_SSP1_Tx: SSP1, Tx
+ - GPDMA_CONN_SSP1_Rx: SSP1, Rx
+ - GPDMA_CONN_ADC: ADC
+ - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
+ - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
+ - GPDMA_CONN_DAC: DAC
+ - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
+ - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
+ - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
+ - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
+ - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
+ - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
+ - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
+ - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
+ */
+ uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
+ following:
+ - GPDMA_CONN_SSP0_Tx: SSP0, Tx
+ - GPDMA_CONN_SSP0_Rx: SSP0, Rx
+ - GPDMA_CONN_SSP1_Tx: SSP1, Tx
+ - GPDMA_CONN_SSP1_Rx: SSP1, Rx
+ - GPDMA_CONN_ADC: ADC
+ - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
+ - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
+ - GPDMA_CONN_DAC: DAC
+ - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
+ - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
+ - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
+ - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
+ - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
+ - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
+ - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
+ - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
+ */
+ uint32_t DMALLI; /**< Linker List Item structure data address
+ if there's no Linker List, set as '0'
+ */
+} GPDMA_Channel_CFG_Type;
+
+/**
+ * @brief GPDMA Linker List Item structure type definition
+ */
+typedef struct {
+ uint32_t SrcAddr; /**< Source Address */
+ uint32_t DstAddr; /**< Destination address */
+ uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
+ uint32_t Control; /**< GPDMA Control of this LLI */
+} GPDMA_LLI_Type;
+
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
+ * @{
+ */
+
+void GPDMA_Init(void);
+//Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs);
+Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
+IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
+void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
+void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
+//void GPDMA_IntHandler(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_GPDMA_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_gpio.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_gpio.h new file mode 100644 index 0000000..1cca9d0 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_gpio.h @@ -0,0 +1,165 @@ +/***********************************************************************//**
+ * @file lpc17xx_gpio.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for GPIO firmware library on LPC17xx
+ * @version 3.0
+ * @date 18. June. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup GPIO GPIO
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_GPIO_H_
+#define LPC17XX_GPIO_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup GPIO_Public_Macros GPIO Public Macros
+ * @{
+ */
+
+/** Fast GPIO port 0 byte accessible definition */
+#define GPIO0_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO0_BASE))
+/** Fast GPIO port 1 byte accessible definition */
+#define GPIO1_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO1_BASE))
+/** Fast GPIO port 2 byte accessible definition */
+#define GPIO2_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO2_BASE))
+/** Fast GPIO port 3 byte accessible definition */
+#define GPIO3_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO3_BASE))
+/** Fast GPIO port 4 byte accessible definition */
+#define GPIO4_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO4_BASE))
+
+
+/** Fast GPIO port 0 half-word accessible definition */
+#define GPIO0_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO0_BASE))
+/** Fast GPIO port 1 half-word accessible definition */
+#define GPIO1_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO1_BASE))
+/** Fast GPIO port 2 half-word accessible definition */
+#define GPIO2_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO2_BASE))
+/** Fast GPIO port 3 half-word accessible definition */
+#define GPIO3_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO3_BASE))
+/** Fast GPIO port 4 half-word accessible definition */
+#define GPIO4_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO4_BASE))
+
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup GPIO_Public_Types GPIO Public Types
+ * @{
+ */
+
+/**
+ * @brief Fast GPIO port byte type definition
+ */
+typedef struct {
+ __IO uint8_t FIODIR[4]; /**< FIO direction register in byte-align */
+ uint32_t RESERVED0[3]; /**< Reserved */
+ __IO uint8_t FIOMASK[4]; /**< FIO mask register in byte-align */
+ __IO uint8_t FIOPIN[4]; /**< FIO pin register in byte align */
+ __IO uint8_t FIOSET[4]; /**< FIO set register in byte-align */
+ __O uint8_t FIOCLR[4]; /**< FIO clear register in byte-align */
+} GPIO_Byte_TypeDef;
+
+
+/**
+ * @brief Fast GPIO port half-word type definition
+ */
+typedef struct {
+ __IO uint16_t FIODIRL; /**< FIO direction register lower halfword part */
+ __IO uint16_t FIODIRU; /**< FIO direction register upper halfword part */
+ uint32_t RESERVED0[3]; /**< Reserved */
+ __IO uint16_t FIOMASKL; /**< FIO mask register lower halfword part */
+ __IO uint16_t FIOMASKU; /**< FIO mask register upper halfword part */
+ __IO uint16_t FIOPINL; /**< FIO pin register lower halfword part */
+ __IO uint16_t FIOPINU; /**< FIO pin register upper halfword part */
+ __IO uint16_t FIOSETL; /**< FIO set register lower halfword part */
+ __IO uint16_t FIOSETU; /**< FIO set register upper halfword part */
+ __O uint16_t FIOCLRL; /**< FIO clear register lower halfword part */
+ __O uint16_t FIOCLRU; /**< FIO clear register upper halfword part */
+} GPIO_HalfWord_TypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup GPIO_Public_Functions GPIO Public Functions
+ * @{
+ */
+
+/* GPIO style ------------------------------- */
+void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
+void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
+void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
+uint32_t GPIO_ReadValue(uint8_t portNum);
+void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
+FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
+void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
+
+/* FIO (word-accessible) style ------------------------------- */
+void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
+void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
+void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
+uint32_t FIO_ReadValue(uint8_t portNum);
+void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
+void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
+FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
+void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
+
+/* FIO (halfword-accessible) style ------------------------------- */
+void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir);
+void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue);
+void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
+void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
+uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum);
+
+/* FIO (byte-accessible) style ------------------------------- */
+void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir);
+void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue);
+void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
+void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
+uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_GPIO_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_i2c.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_i2c.h new file mode 100644 index 0000000..ad374f6 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_i2c.h @@ -0,0 +1,377 @@ +/***********************************************************************//**
+ * @file lpc17xx_i2c.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for I2C firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup I2C I2C
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_I2C_H_
+#define LPC17XX_I2C_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup I2C_Private_Macros I2C Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*******************************************************************//**
+ * I2C Control Set register description
+ *********************************************************************/
+#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
+#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
+#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
+#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
+#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
+
+/*******************************************************************//**
+ * I2C Control Clear register description
+ *********************************************************************/
+/** Assert acknowledge Clear bit */
+#define I2C_I2CONCLR_AAC ((1<<2))
+/** I2C interrupt Clear bit */
+#define I2C_I2CONCLR_SIC ((1<<3))
+/** START flag Clear bit */
+#define I2C_I2CONCLR_STAC ((1<<5))
+/** I2C interface Disable bit */
+#define I2C_I2CONCLR_I2ENC ((1<<6))
+
+/********************************************************************//**
+ * I2C Status Code definition (I2C Status register)
+ *********************************************************************/
+/* Return Code in I2C status register */
+#define I2C_STAT_CODE_BITMASK ((0xF8))
+
+/* I2C return status code definitions ----------------------------- */
+
+/** No relevant information */
+#define I2C_I2STAT_NO_INF ((0xF8))
+
+/* Master transmit mode -------------------------------------------- */
+/** A start condition has been transmitted */
+#define I2C_I2STAT_M_TX_START ((0x08))
+/** A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_TX_RESTART ((0x10))
+/** SLA+W has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
+/** SLA+W has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
+/** Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
+/** Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
+/** Arbitration lost in SLA+R/W or Data bytes */
+#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
+
+/* Master receive mode -------------------------------------------- */
+/** A start condition has been transmitted */
+#define I2C_I2STAT_M_RX_START ((0x08))
+/** A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_RX_RESTART ((0x10))
+/** Arbitration lost */
+#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
+/** SLA+R has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
+/** SLA+R has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
+/** Data has been received, ACK has been returned */
+#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
+/** Data has been received, NACK has been return */
+#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
+
+/* Slave receive mode -------------------------------------------- */
+/** Own slave address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
+
+/** Arbitration lost in SLA+R/W as master */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
+/** Own SLA+W has been received, ACK returned */
+//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
+
+/** General call address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
+
+/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
+/** General call address has been received, ACK has been returned */
+//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
+
+/** Previously addressed with own SLV address;
+ * Data has been received, ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
+/** Previously addressed with own SLA;
+ * Data has been received and NOT ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
+/** Previously addressed with General Call;
+ * Data has been received and ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
+/** Previously addressed with General Call;
+ * Data has been received and NOT ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
+/** A STOP condition or repeated START condition has
+ * been received while still addressed as SLV/REC
+ * (Slave Receive) or SLV/TRX (Slave Transmit) */
+#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
+
+/** Slave transmit mode */
+/** Own SLA+R has been received, ACK has been returned */
+#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
+
+/** Arbitration lost in SLA+R/W as master */
+#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
+/** Own SLA+R has been received, ACK has been returned */
+//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
+
+/** Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
+/** Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
+/** Last data byte in I2DAT has been transmitted (AA = 0);
+ ACK has been received */
+#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
+
+/** Time out in case of using I2C slave mode */
+#define I2C_SLAVE_TIME_OUT 0x10000UL
+
+/********************************************************************//**
+ * I2C Data register definition
+ *********************************************************************/
+/** Mask for I2DAT register*/
+#define I2C_I2DAT_BITMASK ((0xFF))
+
+/** Idle data value will be send out in slave mode in case of the actual
+ * expecting data requested from the master is greater than its sending data
+ * length that can be supported */
+#define I2C_I2DAT_IDLE_CHAR (0xFF)
+
+/********************************************************************//**
+ * I2C Monitor mode control register description
+ *********************************************************************/
+#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
+#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
+#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
+#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
+
+/********************************************************************//**
+ * I2C Data buffer register description
+ *********************************************************************/
+/** I2C Data buffer register bit mask */
+#define I2DATA_BUFFER_BITMASK ((0xFF))
+
+/********************************************************************//**
+ * I2C Slave Address registers definition
+ *********************************************************************/
+/** General Call enable bit */
+#define I2C_I2ADR_GC ((1<<0))
+/** I2C Slave Address registers bit mask */
+#define I2C_I2ADR_BITMASK ((0xFF))
+
+/********************************************************************//**
+ * I2C Mask Register definition
+ *********************************************************************/
+/** I2C Mask Register mask field */
+#define I2C_I2MASK_MASK(n) ((n&0xFE))
+
+/********************************************************************//**
+ * I2C SCL HIGH duty cycle Register definition
+ *********************************************************************/
+/** I2C SCL HIGH duty cycle Register bit mask */
+#define I2C_I2SCLH_BITMASK ((0xFFFF))
+
+/********************************************************************//**
+ * I2C SCL LOW duty cycle Register definition
+ *********************************************************************/
+/** I2C SCL LOW duty cycle Register bit mask */
+#define I2C_I2SCLL_BITMASK ((0xFFFF))
+
+/* I2C status values */
+#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
+#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
+#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
+
+/*********************************************************************//**
+ * I2C monitor control configuration defines
+ **********************************************************************/
+#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
+#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macros check I2C slave address */
+#define PARAM_I2C_SLAVEADDR_CH(n) ((n>=0) && (n<=3))
+
+/** Macro to determine if it is valid SSP port number */
+#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_I2C2)))
+
+/* Macros check I2C monitor configuration type */
+#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
+
+/**
+ * @}
+ */
+
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup I2C_Public_Types I2C Public Types
+ * @{
+ */
+
+/**
+ * @brief I2C Own slave address setting structure + */
+typedef struct {
+ uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
+ should be in range from 0..3
+ */
+ uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
+ uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
+ when I2C control being in Slave mode, should be:
+ - ENABLE: Enable General Call function.
+ - DISABLE: Disable General Call function.
+ */
+ uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
+ which is set to '1' will cause an automatic compare on
+ the corresponding bit of the received address when it
+ is compared to the SlaveAddr_7bit value associated with this
+ mask register. In other words, bits in SlaveAddr_7bit value
+ which are masked are not taken into account in determining
+ an address match
+ */
+} I2C_OWNSLAVEADDR_CFG_Type;
+
+
+/**
+ * @brief Master transfer setup data structure definitions
+ */
+typedef struct
+{
+ uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
+ uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
+ is not used */
+ uint32_t tx_length; /**< Transmit data length - 0 if data transmit
+ is not used*/
+ uint32_t tx_count; /**< Current Transmit data counter */
+ uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
+ is not used */
+ uint32_t rx_length; /**< Receive data length - 0 if data receive is
+ not used */
+ uint32_t rx_count; /**< Current Receive data counter */
+ uint32_t retransmissions_max; /**< Max Re-Transmission value */
+ uint32_t retransmissions_count; /**< Current Re-Transmission counter */
+ uint32_t status; /**< Current status of I2C activity */
+ void (*callback)(void); /**< Pointer to Call back function when transmission complete
+ used in interrupt transfer mode */
+} I2C_M_SETUP_Type;
+
+
+/**
+ * @brief Slave transfer setup data structure definitions
+ */
+typedef struct
+{
+ uint8_t* tx_data;
+ uint32_t tx_length;
+ uint32_t tx_count;
+ uint8_t* rx_data;
+ uint32_t rx_length;
+ uint32_t rx_count;
+ uint32_t status;
+ void (*callback)(void);
+} I2C_S_SETUP_Type;
+
+/**
+ * @brief Transfer option type definitions
+ */
+typedef enum {
+ I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
+ I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
+} I2C_TRANSFER_OPT_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup I2C_Public_Functions I2C Public Functions
+ * @{
+ */
+
+/* I2C Init/DeInit functions ---------- */
+void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate);
+void I2C_DeInit(LPC_I2C_TypeDef* I2Cx);
+//void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock);
+void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* I2C transfer data functions -------- */
+Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \
+ I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \
+ I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+uint32_t I2C_MasterTransferComplete(LPC_I2C_TypeDef *I2Cx);
+uint32_t I2C_SlaveTransferComplete(LPC_I2C_TypeDef *I2Cx);
+
+
+void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
+uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx);
+
+/* I2C Monitor functions ---------------*/
+void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
+void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState);
+uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx);
+BOOL_8 I2C_MonitorHandler(LPC_I2C_TypeDef *I2Cx, uint8_t *buffer, uint32_t size);
+
+/* I2C Interrupt handler functions ------*/
+void I2C_IntCmd (LPC_I2C_TypeDef *I2Cx, Bool NewState);
+void I2C_MasterHandler (LPC_I2C_TypeDef *I2Cx);
+void I2C_SlaveHandler (LPC_I2C_TypeDef *I2Cx);
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_I2C_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_i2s.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_i2s.h new file mode 100644 index 0000000..42ee8a9 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_i2s.h @@ -0,0 +1,372 @@ +/***********************************************************************//**
+ * @file lpc17xx_i2s.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for I2S firmware library on LPC17xx
+ * @version 3.0
+ * @date 18. June. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup I2S I2S
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_I2S_H_
+#define LPC17XX_I2S_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup I2S_Public_Macros I2S Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * I2S configuration parameter defines
+ **********************************************************************/
+/** I2S Wordwidth bit */
+#define I2S_WORDWIDTH_8 ((uint32_t)(0))
+#define I2S_WORDWIDTH_16 ((uint32_t)(1))
+#define I2S_WORDWIDTH_32 ((uint32_t)(3))
+/** I2S Channel bit */
+#define I2S_STEREO ((uint32_t)(0))
+#define I2S_MONO ((uint32_t)(1))
+/** I2S Master/Slave mode bit */
+#define I2S_MASTER_MODE ((uint8_t)(0))
+#define I2S_SLAVE_MODE ((uint8_t)(1))
+/** I2S Stop bit */
+#define I2S_STOP_ENABLE ((uint8_t)(1))
+#define I2S_STOP_DISABLE ((uint8_t)(0))
+/** I2S Reset bit */
+#define I2S_RESET_ENABLE ((uint8_t)(1))
+#define I2S_RESET_DISABLE ((uint8_t)(0))
+/** I2S Mute bit */
+#define I2S_MUTE_ENABLE ((uint8_t)(1))
+#define I2S_MUTE_DISABLE ((uint8_t)(0))
+/** I2S Transmit/Receive bit */
+#define I2S_TX_MODE ((uint8_t)(0))
+#define I2S_RX_MODE ((uint8_t)(1))
+/** I2S Clock Select bit */
+#define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
+#define I2S_CLKSEL_MCLK ((uint8_t)(2))
+/** I2S 4-pin Mode bit */
+#define I2S_4PIN_ENABLE ((uint8_t)(1))
+#define I2S_4PIN_DISABLE ((uint8_t)(0))
+/** I2S MCLK Enable bit */
+#define I2S_MCLK_ENABLE ((uint8_t)(1))
+#define I2S_MCLK_DISABLE ((uint8_t)(0))
+/** I2S select DMA bit */
+#define I2S_DMA_1 ((uint8_t)(0))
+#define I2S_DMA_2 ((uint8_t)(1))
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * Macro defines for DAO-Digital Audio Output register
+ **********************************************************************/
+/** I2S wordwide - the number of bytes in data*/
+#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
+#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
+#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
+/** I2S control mono or stereo format */
+#define I2S_DAO_MONO ((uint32_t)(1<<2))
+/** I2S control stop mode */
+#define I2S_DAO_STOP ((uint32_t)(1<<3))
+/** I2S control reset mode */
+#define I2S_DAO_RESET ((uint32_t)(1<<4))
+/** I2S control master/slave mode */
+#define I2S_DAO_SLAVE ((uint32_t)(1<<5))
+/** I2S word select half period minus one */
+#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
+/** I2S control mute mode */
+#define I2S_DAO_MUTE ((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for DAI-Digital Audio Input register
+**********************************************************************/
+/** I2S wordwide - the number of bytes in data*/
+#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
+#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
+#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
+/** I2S control mono or stereo format */
+#define I2S_DAI_MONO ((uint32_t)(1<<2))
+/** I2S control stop mode */
+#define I2S_DAI_STOP ((uint32_t)(1<<3))
+/** I2S control reset mode */
+#define I2S_DAI_RESET ((uint32_t)(1<<4))
+/** I2S control master/slave mode */
+#define I2S_DAI_SLAVE ((uint32_t)(1<<5))
+/** I2S word select half period minus one (9 bits)*/
+#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
+/** I2S control mute mode */
+#define I2S_DAI_MUTE ((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for STAT register (Status Feedback register)
+**********************************************************************/
+/** I2S Status Receive or Transmit Interrupt */
+#define I2S_STATE_IRQ ((uint32_t)(1))
+/** I2S Status Receive or Transmit DMA1 */
+#define I2S_STATE_DMA1 ((uint32_t)(1<<1))
+/** I2S Status Receive or Transmit DMA2 */
+#define I2S_STATE_DMA2 ((uint32_t)(1<<2))
+/** I2S Status Current level of the Receive FIFO (5 bits)*/
+#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
+/** I2S Status Current level of the Transmit FIFO (5 bits)*/
+#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
+
+/*********************************************************************//**
+ * Macro defines for DMA1 register (DMA1 Configuration register)
+**********************************************************************/
+/** I2S control DMA1 for I2S receive */
+#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
+/** I2S control DMA1 for I2S transmit */
+#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
+/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
+/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
+
+/*********************************************************************//**
+ * Macro defines for DMA2 register (DMA2 Configuration register)
+**********************************************************************/
+/** I2S control DMA2 for I2S receive */
+#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
+/** I2S control DMA1 for I2S transmit */
+#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
+/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
+/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
+
+/*********************************************************************//**
+* Macro defines for IRQ register (Interrupt Request Control register)
+**********************************************************************/
+/** I2S control I2S receive interrupt */
+#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
+/** I2S control I2S transmit interrupt */
+#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
+/** I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
+/** I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
+
+/********************************************************************************//**
+ * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
+*********************************************************************************/
+/** I2S Transmit MCLK rate denominator */
+#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
+/** I2S Transmit MCLK rate denominator */
+#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
+/** I2S Receive MCLK rate denominator */
+#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
+/** I2S Receive MCLK rate denominator */
+#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
+
+/*************************************************************************************//**
+ * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
+**************************************************************************************/
+#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
+#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
+
+/**********************************************************************************//**
+ * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
+************************************************************************************/
+/** I2S Transmit select clock source (2 bits)*/
+#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
+/** I2S Transmit control 4-pin mode */
+#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
+/** I2S Transmit control the TX_MCLK output */
+#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
+/** I2S Receive select clock source */
+#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
+/** I2S Receive control 4-pin mode */
+#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
+/** I2S Receive control the TX_MCLK output */
+#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid I2S peripheral */
+#define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S))
+/** Macro to check Data to send valid */
+#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
+/* Macro check I2S word width type */
+#define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
+||(n==I2S_WORDWIDTH_32))
+/* Macro check I2S channel type */
+#define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
+/* Macro check I2S master/slave mode */
+#define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
+/* Macro check I2S stop mode */
+#define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
+/* Macro check I2S reset mode */
+#define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
+/* Macro check I2S reset mode */
+#define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
+/* Macro check I2S transmit/receive mode */
+#define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
+/* Macro check I2S clock select mode */
+#define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
+/* Macro check I2S 4-pin mode */
+#define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
+/* Macro check I2S MCLK mode */
+#define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
+/* Macro check I2S DMA mode */
+#define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
+/* Macro check I2S DMA depth value */
+#define PARAM_I2S_DMA_DEPTH(n) ((n>=0)||(n<=31))
+/* Macro check I2S irq level value */
+#define PARAM_I2S_IRQ_LEVEL(n) ((n>=0)||(n<=31))
+/* Macro check I2S half-period value */
+#define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512))
+/* Macro check I2S bit-rate value */
+#define PARAM_I2S_BITRATE(n) ((n>=0)&&(n<=63))
+/**
+ * @}
+ */
+
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup I2S_Public_Types I2S Public Types
+ * @{
+ */
+
+/**
+ * @brief I2S configuration structure definition
+ */
+typedef struct {
+ uint8_t wordwidth; /** the number of bytes in data as follow:
+ -I2S_WORDWIDTH_8: 8 bit data
+ -I2S_WORDWIDTH_16: 16 bit data
+ -I2S_WORDWIDTH_32: 32 bit data */
+ uint8_t mono; /** Set mono/stereo mode, should be:
+ - I2S_STEREO: stereo mode
+ - I2S_MONO: mono mode */
+ uint8_t stop; /** Disables accesses on FIFOs, should be:
+ - I2S_STOP_ENABLE: enable stop mode
+ - I2S_STOP_DISABLE: disable stop mode */
+ uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
+ - I2S_RESET_ENABLE: enable reset mode
+ - I2S_RESET_DISABLE: disable reset mode */
+ uint8_t ws_sel; /** Set Master/Slave mode, should be:
+ - I2S_MASTER_MODE: I2S master mode
+ - I2S_SLAVE_MODE: I2S slave mode */
+ uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
+ - I2S_MUTE_ENABLE: enable mute mode
+ - I2S_MUTE_DISABLE: disable mute mode */
+ uint8_t Reserved0[2];
+} I2S_CFG_Type;
+
+/**
+ * @brief I2S DMA configuration structure definition
+ */
+typedef struct {
+ uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
+ - I2S_DMA_1: DMA1
+ - I2S_DMA_2: DMA2 */
+ uint8_t depth; /** FIFO level that triggers a DMA request */
+ uint8_t Reserved0[2];
+}I2S_DMAConf_Type;
+
+/**
+ * @brief I2S mode configuration structure definition
+ */
+typedef struct{
+ uint8_t clksel; /** Clock source selection, should be:
+ - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
+ - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
+ uint8_t fpin; /** Select four pin mode, should be:
+ - I2S_4PIN_ENABLE: 4-pin enable
+ - I2S_4PIN_DISABLE: 4-pin disable */
+ uint8_t mcena; /** Select MCLK mode, should be:
+ - I2S_MCLK_ENABLE: MCLK enable for output
+ - I2S_MCLK_DISABLE: MCLK disable for output */
+ uint8_t Reserved;
+}I2S_MODEConf_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup I2S_Public_Functions I2S Public Functions
+ * @{
+ */
+/* I2S Init/DeInit functions ---------*/
+void I2S_Init(LPC_I2S_TypeDef *I2Sx);
+void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
+
+/* I2S configuration functions --------*/
+void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
+Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
+void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
+void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
+uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+
+/* I2S operate functions -------------*/
+void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
+uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
+void I2S_Start(LPC_I2S_TypeDef *I2Sx);
+void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+
+/* I2S DMA functions ----------------*/
+void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
+void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
+
+/* I2S IRQ functions ----------------*/
+void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
+void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
+FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
+uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_SSP_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_libcfg_default.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_libcfg_default.h new file mode 100644 index 0000000..ee8ddf3 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_libcfg_default.h @@ -0,0 +1,170 @@ +/***********************************************************************//**
+ * @file lpc17xx_libcfg_default.h
+ * @brief Default Library configuration header file
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Library Configuration group ----------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_LIBCFG_DEFAULT_H_
+#define LPC17XX_LIBCFG_DEFAULT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc_types.h"
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros
+ * @{
+ */
+
+/************************** DEBUG MODE DEFINITIONS *********************************/
+/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
+ the "CHECK_PARAM" macro in the FW library code */
+
+#define DEBUG
+
+
+/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
+/* Comment the line below to disable the specific peripheral inclusion */
+
+/* DEBUG_FRAMWORK ------------------------------ */
+#define _DBGFWK
+
+/* GPIO ------------------------------- */
+#define _GPIO
+
+/* EXTI ------------------------------- */
+#define _EXTI
+
+/* UART ------------------------------- */
+#define _UART
+#define _UART0
+#define _UART1
+#define _UART2
+#define _UART3
+
+/* SPI ------------------------------- */
+#define _SPI
+
+/* SYSTICK --------------------------- */
+#define _SYSTICK
+
+/* SSP ------------------------------- */
+#define _SSP
+#define _SSP0
+#define _SSP1
+
+
+/* I2C ------------------------------- */
+#define _I2C
+#define _I2C0
+#define _I2C1
+#define _I2C2
+
+/* TIMER ------------------------------- */
+#define _TIM
+
+/* WDT ------------------------------- */
+#define _WDT
+
+
+/* GPDMA ------------------------------- */
+#define _GPDMA
+
+
+/* DAC ------------------------------- */
+#define _DAC
+
+/* DAC ------------------------------- */
+#define _ADC
+
+
+/* PWM ------------------------------- */
+#define _PWM
+#define _PWM1
+
+/* RTC ------------------------------- */
+#define _RTC
+
+/* I2S ------------------------------- */
+#define _I2S
+
+/* USB device ------------------------------- */
+#define _USBDEV
+#define _USB_DMA
+
+/* QEI ------------------------------- */
+#define _QEI
+
+/* MCPWM ------------------------------- */
+#define _MCPWM
+
+/* CAN--------------------------------*/
+#define _CAN
+
+/* RIT ------------------------------- */
+#define _RIT
+
+/* EMAC ------------------------------ */
+#define _EMAC
+
+/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
+
+#ifdef DEBUG
+/*******************************************************************************
+* @brief The CHECK_PARAM macro is used for function's parameters check.
+* It is used only if the library is compiled in DEBUG mode.
+* @param[in] expr - If expr is false, it calls check_failed() function
+* which reports the name of the source file and the source
+* line number of the call that failed.
+* - If expr is true, it returns no value.
+* @return None
+*******************************************************************************/
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr)
+#endif /* DEBUG */
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions
+ * @{
+ */
+
+#ifdef DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LPC17XX_LIBCFG_DEFAULT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_mcpwm.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_mcpwm.h new file mode 100644 index 0000000..48bc074 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_mcpwm.h @@ -0,0 +1,317 @@ +/***********************************************************************//**
+ * @file lpc17xx_mcpwm.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for Motor Control PWM firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup MCPWM MCPWM
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_MCPWM_H_
+#define LPC17XX_MCPWM_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup MCPWM_Public_Macros MCPWM Public Macros
+ * @{
+ */
+
+
+/** Edge aligned mode for channel in MCPWM */
+#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))
+/** Center aligned mode for channel in MCPWM */
+#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))
+
+/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
+#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))
+/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
+#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))
+
+/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
+ * the six output pins under the control of the bits in this register */
+#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
+#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
+#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
+#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
+#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
+#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
+
+/* Interrupt type in MCPWM */
+/** Limit interrupt for channel (0) */
+#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)
+/** Match interrupt for channel (0) */
+#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)
+/** Capture interrupt for channel (0) */
+#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)
+
+/** Limit interrupt for channel (1) */
+#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)
+/** Match interrupt for channel (1) */
+#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)
+/** Capture interrupt for channel (1) */
+#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)
+
+/** Limit interrupt for channel (2) */
+#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)
+/** Match interrupt for channel (2) */
+#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)
+/** Capture interrupt for channel (2) */
+#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)
+
+/** Fast abort interrupt */
+#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup MCPWM_Private_Macros MCPWM Private Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Control register
+ **********************************************************************/
+/* MCPWM Control register, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Control read address
+ * - MCPWM Control set address
+ * - MCPWM Control clear address
+ */
+#define MCPWM_CON_RUN(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0)) /**< Stops/starts timer channel n */
+#define MCPWM_CON_CENTER(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0)) /**< Edge/center aligned operation for channel n */
+#define MCPWM_CON_POLAR(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0)) /**< Select polarity of the MCOAn and MCOBn pin */
+#define MCPWM_CON_DTE(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0)) /**< Control the dead-time feature for channel n */
+#define MCPWM_CON_DISUP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0)) /**< Enable/Disable update of functional register for channel n */
+#define MCPWM_CON_INVBDC ((uint32_t)(1<<29)) /**< Control the polarity for all 3 channels */
+#define MCPWM_CON_ACMODE ((uint32_t)(1<<30)) /**< 3-phase AC mode select */
+#define MCPWM_CON_DCMODE ((uint32_t)(1<<31)) /**< 3-phase DC mode select */
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Capture Control register
+ **********************************************************************/
+/* Capture Control register, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Capture Control read address
+ * - MCPWM Capture Control set address
+ * - MCPWM Capture control clear address
+ */
+/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
+#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap>=0)&&(cap<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
+/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
+#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap>=0)&&(cap<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
+/** TC(n) is reset by channel (n) capture event */
+#define MCPWM_CAPCON_RT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0))
+/** Hardware noise filter: channel (n) capture events are delayed */
+#define MCPWM_CAPCON_HNFCAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Interrupt register
+ **********************************************************************/
+/* Interrupt registers, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Interrupt Enable read address
+ * - MCPWM Interrupt Enable set address
+ * - MCPWM Interrupt Enable clear address
+ * - MCPWM Interrupt Flags read address
+ * - MCPWM Interrupt Flags set address
+ * - MCPWM Interrupt Flags clear address
+ */
+/** Limit interrupt for channel (n) */
+#define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))
+/** Match interrupt for channel (n) */
+#define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))
+/** Capture interrupt for channel (n) */
+#define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))
+/** Fast abort interrupt */
+#define MCPWM_INT_ABORT ((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Count Control register
+ **********************************************************************/
+/* MCPWM Count Control register, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Count Control read address
+ * - MCPWM Count Control set address
+ * - MCPWM Count Control clear address
+ */
+/** Counter(tc) advances on a rising edge on MCI(mci) pin */
+#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc>=0)&&(tc<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
+/** Counter(cnt) advances on a falling edge on MCI(mci) pin */
+#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc>=0)&&(tc<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
+/** Channel (n) is in counter mode */
+#define MCPWM_CNTCON_CNTR(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(29+n))) : (0))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Dead-time register
+ **********************************************************************/
+/** Dead time value x for channel n */
+#define MCPWM_DT(n,x) (((n>=0)&&(n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Communication Pattern register
+ **********************************************************************/
+#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
+#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
+#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
+#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
+#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
+#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Capture clear address register
+ **********************************************************************/
+/** Clear the MCCAP (n) register */
+#define MCPWM_CAPCLR_CAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<n)) : (0))
+
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup MCPWM_Public_Types MCPWM Public Types
+ * @{
+ */
+
+/**
+ * @brief Motor Control PWM Channel Configuration structure type definition
+ */
+typedef struct {
+ uint32_t channelType; /**< Edge/center aligned mode for this channel,
+ should be:
+ - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
+ - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
+ */
+ uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be:
+ - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
+ - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
+ */
+ uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */
+ uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers,
+ should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */
+ uint32_t channelPeriodValue; /**< MCPWM Period value */
+ uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */
+} MCPWM_CHANNEL_CFG_Type;
+
+/**
+ * @brief MCPWM Capture Configuration type definition
+ */
+typedef struct {
+ uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */
+ uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+} MCPWM_CAPTURE_CFG_Type;
+
+
+/**
+ * @brief MCPWM Count Control Configuration type definition
+ */
+typedef struct {
+ uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */
+ uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+} MCPWM_COUNT_CFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup MCPWM_Public_Functions MCPWM Public Functions
+ * @{
+ */
+
+void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx);
+void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ MCPWM_CHANNEL_CFG_Type * channelSetup);
+void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ MCPWM_CHANNEL_CFG_Type *channelSetup);
+void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ MCPWM_CAPTURE_CFG_Type *captureConfig);
+void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
+uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
+void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
+void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
+void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
+void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode);
+void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
+ uint32_t outputInvered, uint32_t outputPattern);
+void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
+void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
+void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
+FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_MCPWM_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_nvic.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_nvic.h new file mode 100644 index 0000000..e6bcf3b --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_nvic.h @@ -0,0 +1,64 @@ +/***********************************************************************//**
+ * @file lpc17xx_nvic.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for Nesting Vectored Interrupt firmware library
+ * on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup NVIC NVIC
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_NVIC_H_
+#define LPC17XX_NVIC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup NVIC_Public_Functions NVIC Public Functions
+ * @{
+ */
+
+void NVIC_DeInit(void);
+void NVIC_SCBDeInit(void);
+void NVIC_SetVTOR(uint32_t offset);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_NVIC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_pinsel.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_pinsel.h new file mode 100644 index 0000000..f8c47b9 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_pinsel.h @@ -0,0 +1,191 @@ +/***********************************************************************//**
+ * @file lpc17xx_pinsel.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for Pin connect block firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup PINSEL PINSEL
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_PINSEL_H_
+#define LPC17XX_PINSEL_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Macros PINSEL Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ *!< Macros define for PORT Selection
+ ***********************************************************************/
+#define PINSEL_PORT_0 ((0)) /**< PORT 0*/
+#define PINSEL_PORT_1 ((1)) /**< PORT 1*/
+#define PINSEL_PORT_2 ((2)) /**< PORT 2*/
+#define PINSEL_PORT_3 ((3)) /**< PORT 3*/
+#define PINSEL_PORT_4 ((4)) /**< PORT 4*/
+
+/***********************************************************************
+ * Macros define for Pin Function selection
+ **********************************************************************/
+#define PINSEL_FUNC_0 ((0)) /**< default function*/
+#define PINSEL_FUNC_1 ((1)) /**< first alternate function*/
+#define PINSEL_FUNC_2 ((2)) /**< second alternate function*/
+#define PINSEL_FUNC_3 ((3)) /**< third or reserved alternate function*/
+
+/***********************************************************************
+ * Macros define for Pin Number of Port
+ **********************************************************************/
+#define PINSEL_PIN_0 ((0)) /**< Pin 0 */
+#define PINSEL_PIN_1 ((1)) /**< Pin 1 */
+#define PINSEL_PIN_2 ((2)) /**< Pin 2 */
+#define PINSEL_PIN_3 ((3)) /**< Pin 3 */
+#define PINSEL_PIN_4 ((4)) /**< Pin 4 */
+#define PINSEL_PIN_5 ((5)) /**< Pin 5 */
+#define PINSEL_PIN_6 ((6)) /**< Pin 6 */
+#define PINSEL_PIN_7 ((7)) /**< Pin 7 */
+#define PINSEL_PIN_8 ((8)) /**< Pin 8 */
+#define PINSEL_PIN_9 ((9)) /**< Pin 9 */
+#define PINSEL_PIN_10 ((10)) /**< Pin 10 */
+#define PINSEL_PIN_11 ((11)) /**< Pin 11 */
+#define PINSEL_PIN_12 ((12)) /**< Pin 12 */
+#define PINSEL_PIN_13 ((13)) /**< Pin 13 */
+#define PINSEL_PIN_14 ((14)) /**< Pin 14 */
+#define PINSEL_PIN_15 ((15)) /**< Pin 15 */
+#define PINSEL_PIN_16 ((16)) /**< Pin 16 */
+#define PINSEL_PIN_17 ((17)) /**< Pin 17 */
+#define PINSEL_PIN_18 ((18)) /**< Pin 18 */
+#define PINSEL_PIN_19 ((19)) /**< Pin 19 */
+#define PINSEL_PIN_20 ((20)) /**< Pin 20 */
+#define PINSEL_PIN_21 ((21)) /**< Pin 21 */
+#define PINSEL_PIN_22 ((22)) /**< Pin 22 */
+#define PINSEL_PIN_23 ((23)) /**< Pin 23 */
+#define PINSEL_PIN_24 ((24)) /**< Pin 24 */
+#define PINSEL_PIN_25 ((25)) /**< Pin 25 */
+#define PINSEL_PIN_26 ((26)) /**< Pin 26 */
+#define PINSEL_PIN_27 ((27)) /**< Pin 27 */
+#define PINSEL_PIN_28 ((28)) /**< Pin 28 */
+#define PINSEL_PIN_29 ((29)) /**< Pin 29 */
+#define PINSEL_PIN_30 ((30)) /**< Pin 30 */
+#define PINSEL_PIN_31 ((31)) /**< Pin 31 */
+
+/***********************************************************************
+ * Macros define for Pin mode
+ **********************************************************************/
+#define PINSEL_PINMODE_PULLUP ((0)) /**< Internal pull-up resistor*/
+#define PINSEL_PINMODE_TRISTATE ((2)) /**< Tri-state */
+#define PINSEL_PINMODE_PULLDOWN ((3)) /**< Internal pull-down resistor */
+
+/***********************************************************************
+ * Macros define for Pin mode (normal/open drain)
+ **********************************************************************/
+#define PINSEL_PINMODE_NORMAL ((0)) /**< Pin is in the normal (not open drain) mode.*/
+#define PINSEL_PINMODE_OPENDRAIN ((1)) /**< Pin is in the open drain mode */
+
+/***********************************************************************
+ * Macros define for I2C mode
+ ***********************************************************************/
+#define PINSEL_I2C_Normal_Mode ((0)) /**< The standard drive mode */
+#define PINSEL_I2C_Fast_Mode ((1)) /**< Fast Mode Plus drive mode */
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup PINSEL_Private_Macros PINSEL Private Macros
+ * @{
+ */
+
+/* Pin selection define */
+/* I2C Pin Configuration register bit description */
+#define PINSEL_I2CPADCFG_SDADRV0 _BIT(0) /**< Drive mode control for the SDA0 pin, P0.27 */
+#define PINSEL_I2CPADCFG_SDAI2C0 _BIT(1) /**< I2C mode control for the SDA0 pin, P0.27 */
+#define PINSEL_I2CPADCFG_SCLDRV0 _BIT(2) /**< Drive mode control for the SCL0 pin, P0.28 */
+#define PINSEL_I2CPADCFG_SCLI2C0 _BIT(3) /**< I2C mode control for the SCL0 pin, P0.28 */
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Types PINSEL Public Types
+ * @{
+ */
+
+/** @brief Pin configuration structure */
+typedef struct
+{
+ uint8_t Portnum; /**< Port Number, should be PINSEL_PORT_x,
+ where x should be in range from 0 to 4 */
+ uint8_t Pinnum; /**< Pin Number, should be PINSEL_PIN_x,
+ where x should be in range from 0 to 31 */
+ uint8_t Funcnum; /**< Function Number, should be PINSEL_FUNC_x,
+ where x should be in range from 0 to 3 */
+ uint8_t Pinmode; /**< Pin Mode, should be:
+ - PINSEL_PINMODE_PULLUP: Internal pull-up resistor
+ - PINSEL_PINMODE_TRISTATE: Tri-state
+ - PINSEL_PINMODE_PULLDOWN: Internal pull-down resistor */
+ uint8_t OpenDrain; /**< OpenDrain mode, should be:
+ - PINSEL_PINMODE_NORMAL: Pin is in the normal (not open drain) mode
+ - PINSEL_PINMODE_OPENDRAIN: Pin is in the open drain mode */
+} PINSEL_CFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Functions PINSEL Public Functions
+ * @{
+ */
+
+void PINSEL_ConfigPin(PINSEL_CFG_Type *PinCfg);
+void PINSEL_ConfigTraceFunc (FunctionalState NewState);
+void PINSEL_SetI2C0Pins(uint8_t i2cPinMode, FunctionalState filterSlewRateEnable);
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_PINSEL_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_pwm.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_pwm.h new file mode 100644 index 0000000..db6aafd --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_pwm.h @@ -0,0 +1,330 @@ +/***********************************************************************//**
+ * @file lpc17xx_pwm.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for PWM firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup PWM PWM
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_PWM_H_
+#define LPC17XX_PWM_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup PWM_Private_Macros PWM Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/**********************************************************************
+* IR register definitions
+**********************************************************************/
+/** Interrupt flag for PWM match channel for 6 channel */
+#define PWM_IR_PWMMRn(n) ((uint32_t)((n<4)?(1<<n):(1<<(n+4))))
+/** Interrupt flag for capture input */
+#define PWM_IR_PWMCAPn(n) ((uint32_t)(1<<(n+4)))
+/** IR register mask */
+#define PWM_IR_BITMASK ((uint32_t)(0x0000073F))
+
+/**********************************************************************
+* TCR register definitions
+**********************************************************************/
+/** TCR register mask */
+#define PWM_TCR_BITMASK ((uint32_t)(0x0000000B))
+#define PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0)) /*!< PWM Counter Enable */
+#define PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1)) /*!< PWM Counter Reset */
+#define PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3)) /*!< PWM Enable */
+
+/**********************************************************************
+* CTCR register definitions
+**********************************************************************/
+/** CTCR register mask */
+#define PWM_CTCR_BITMASK ((uint32_t)(0x0000000F))
+/** PWM Counter-Timer Mode */
+#define PWM_CTCR_MODE(n) ((uint32_t)(n&0x03))
+/** PWM Capture input select */
+#define PWM_CTCR_SELECT_INPUT(n) ((uint32_t)((n&0x03)<<2))
+
+/**********************************************************************
+* MCR register definitions
+**********************************************************************/
+/** MCR register mask */
+#define PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF))
+/** generate a PWM interrupt when a MATCHn occurs */
+#define PWM_MCR_INT_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07))))
+/** reset the PWM when a MATCHn occurs */
+#define PWM_MCR_RESET_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1)))
+/** stop the PWM when a MATCHn occurs */
+#define PWM_MCR_STOP_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2)))
+
+/**********************************************************************
+* CCR register definitions
+**********************************************************************/
+/** CCR register mask */
+#define PWM_CCR_BITMASK ((uint32_t)(0x0000003F))
+/** PCAPn is rising edge sensitive */
+#define PWM_CCR_CAP_RISING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1))))
+/** PCAPn is falling edge sensitive */
+#define PWM_CCR_CAP_FALLING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1)))
+/** PWM interrupt is generated on a PCAP event */
+#define PWM_CCR_INT_ON_CAP(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2)))
+
+/**********************************************************************
+* PCR register definitions
+**********************************************************************/
+/** PCR register mask */
+#define PWM_PCR_BITMASK (uint32_t)0x00007E7C
+/** PWM output n is a single edge controlled output */
+#define PWM_PCR_PWMSELn(n) ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n)))
+/** enable PWM output n */
+#define PWM_PCR_PWMENAn(n) ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8))))
+
+/**********************************************************************
+* LER register definitions
+**********************************************************************/
+/** LER register mask*/
+#define PWM_LER_BITMASK ((uint32_t)(0x0000007F))
+/** PWM MATCHn register update control */
+#define PWM_LER_EN_MATCHn_LATCH(n) ((uint32_t)((n<7) ? (1<<n) : 0))
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid PWM peripheral or not */
+#define PARAM_PWMx(n) (((uint32_t *)n)==((uint32_t *)LPC_PWM1))
+
+/** Macro check PWM1 match channel value */
+#define PARAM_PWM1_MATCH_CHANNEL(n) ((n>=0) && (n<=6))
+
+/** Macro check PWM1 channel value */
+#define PARAM_PWM1_CHANNEL(n) ((n>=1) && (n<=6))
+
+/** Macro check PWM1 edge channel mode */
+#define PARAM_PWM1_EDGE_MODE_CHANNEL(n) ((n>=2) && (n<=6))
+
+/** Macro check PWM1 capture channel mode */
+#define PARAM_PWM1_CAPTURE_CHANNEL(n) ((n==0) || (n==1))
+
+/** Macro check PWM1 interrupt status type */
+#define PARAM_PWM_INTSTAT(n) ((n==PWM_INTSTAT_MR0) || (n==PWM_INTSTAT_MR1) || (n==PWM_INTSTAT_MR2) \
+|| (n==PWM_INTSTAT_MR3) || (n==PWM_INTSTAT_MR4) || (n==PWM_INTSTAT_MR5) \
+|| (n==PWM_INTSTAT_MR6) || (n==PWM_INTSTAT_CAP0) || (n==PWM_INTSTAT_CAP1))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup PWM_Public_Types PWM Public Types
+ * @{
+ */
+
+/** @brief Configuration structure in PWM TIMER mode */
+typedef struct {
+
+ uint8_t PrescaleOption; /**< Prescale option, should be:
+ - PWM_TIMER_PRESCALE_TICKVAL: Prescale in absolute value
+ - PWM_TIMER_PRESCALE_USVAL: Prescale in microsecond value
+ */
+ uint8_t Reserved[3];
+ uint32_t PrescaleValue; /**< Prescale value, 32-bit long, should be matched
+ with PrescaleOption
+ */
+} PWM_TIMERCFG_Type;
+
+/** @brief Configuration structure in PWM COUNTER mode */
+typedef struct {
+
+ uint8_t CounterOption; /**< Counter Option, should be:
+ - PWM_COUNTER_RISING: Rising Edge
+ - PWM_COUNTER_FALLING: Falling Edge
+ - PWM_COUNTER_ANY: Both rising and falling mode
+ */
+ uint8_t CountInputSelect; /**< Counter input select, should be:
+ - PWM_COUNTER_PCAP1_0: PWM Counter input selected is PCAP1.0 pin
+ - PWM_COUNTER_PCAP1_1: PWM Counter input selected is PCAP1.1 pin
+ */
+ uint8_t Reserved[2];
+} PWM_COUNTERCFG_Type;
+
+/** @brief PWM Match channel configuration structure */
+typedef struct {
+ uint8_t MatchChannel; /**< Match channel, should be in range
+ from 0..6 */
+ uint8_t IntOnMatch; /**< Interrupt On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+ uint8_t StopOnMatch; /**< Stop On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+ uint8_t ResetOnMatch; /**< Reset On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+} PWM_MATCHCFG_Type;
+
+
+/** @brief PWM Capture Input configuration structure */
+typedef struct {
+ uint8_t CaptureChannel; /**< Capture channel, should be in range
+ from 0..1 */
+ uint8_t RisingEdge; /**< caption rising edge, should be:
+ - ENABLE: Enable rising edge.
+ - DISABLE: Disable this function.
+ */
+ uint8_t FallingEdge; /**< caption falling edge, should be:
+ - ENABLE: Enable falling edge.
+ - DISABLE: Disable this function.
+ */
+ uint8_t IntOnCaption; /**< Interrupt On caption, should be:
+ - ENABLE: Enable interrupt function.
+ - DISABLE: Disable this function.
+ */
+} PWM_CAPTURECFG_Type;
+
+/* Timer/Counter in PWM configuration type definition -----------------------------------*/
+
+/** @brief PMW TC mode select option */
+typedef enum {
+ PWM_MODE_TIMER = 0, /*!< PWM using Timer mode */
+ PWM_MODE_COUNTER, /*!< PWM using Counter mode */
+} PWM_TC_MODE_OPT;
+
+#define PARAM_PWM_TC_MODE(n) ((n==PWM_MODE_TIMER) || (n==PWM_MODE_COUNTER))
+
+
+/** @brief PWM Timer/Counter prescale option */
+typedef enum
+{
+ PWM_TIMER_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */
+ PWM_TIMER_PRESCALE_USVAL /*!< Prescale in microsecond value */
+} PWM_TIMER_PRESCALE_OPT;
+
+#define PARAM_PWM_TIMER_PRESCALE(n) ((n==PWM_TIMER_PRESCALE_TICKVAL) || (n==PWM_TIMER_PRESCALE_USVAL))
+
+
+/** @brief PWM Input Select in counter mode */
+typedef enum {
+ PWM_COUNTER_PCAP1_0 = 0, /*!< PWM Counter input selected is PCAP1.0 pin */
+ PWM_COUNTER_PCAP1_1 /*!< PWM counter input selected is CAP1.1 pin */
+} PWM_COUNTER_INPUTSEL_OPT;
+
+#define PARAM_PWM_COUNTER_INPUTSEL(n) ((n==PWM_COUNTER_PCAP1_0) || (n==PWM_COUNTER_PCAP1_1))
+
+/** @brief PWM Input Edge Option in counter mode */
+typedef enum {
+ PWM_COUNTER_RISING = 1, /*!< Rising edge mode */
+ PWM_COUNTER_FALLING = 2, /*!< Falling edge mode */
+ PWM_COUNTER_ANY = 3 /*!< Both rising and falling mode */
+} PWM_COUNTER_EDGE_OPT;
+
+#define PARAM_PWM_COUNTER_EDGE(n) ((n==PWM_COUNTER_RISING) || (n==PWM_COUNTER_FALLING) \
+|| (n==PWM_COUNTER_ANY))
+
+
+/* PWM configuration type definition ----------------------------------------------------- */
+/** @brief PWM operating mode options */
+typedef enum {
+ PWM_CHANNEL_SINGLE_EDGE, /*!< PWM Channel Single edge mode */
+ PWM_CHANNEL_DUAL_EDGE /*!< PWM Channel Dual edge mode */
+} PWM_CHANNEL_EDGE_OPT;
+
+#define PARAM_PWM_CHANNEL_EDGE(n) ((n==PWM_CHANNEL_SINGLE_EDGE) || (n==PWM_CHANNEL_DUAL_EDGE))
+
+
+/** @brief PWM update type */
+typedef enum {
+ PWM_MATCH_UPDATE_NOW = 0, /**< PWM Match Channel Update Now */
+ PWM_MATCH_UPDATE_NEXT_RST /**< PWM Match Channel Update on next
+ PWM Counter resetting */
+} PWM_MATCH_UPDATE_OPT;
+
+#define PARAM_PWM_MATCH_UPDATE(n) ((n==PWM_MATCH_UPDATE_NOW) || (n==PWM_MATCH_UPDATE_NEXT_RST))
+
+
+/** @brief PWM interrupt status type definition ----------------------------------------------------- */
+/** @brief PWM Interrupt status type */
+typedef enum
+{
+ PWM_INTSTAT_MR0 = PWM_IR_PWMMRn(0), /**< Interrupt flag for PWM match channel 0 */
+ PWM_INTSTAT_MR1 = PWM_IR_PWMMRn(1), /**< Interrupt flag for PWM match channel 1 */
+ PWM_INTSTAT_MR2 = PWM_IR_PWMMRn(2), /**< Interrupt flag for PWM match channel 2 */
+ PWM_INTSTAT_MR3 = PWM_IR_PWMMRn(3), /**< Interrupt flag for PWM match channel 3 */
+ PWM_INTSTAT_CAP0 = PWM_IR_PWMCAPn(0), /**< Interrupt flag for capture input 0 */
+ PWM_INTSTAT_CAP1 = PWM_IR_PWMCAPn(1), /**< Interrupt flag for capture input 1 */
+ PWM_INTSTAT_MR4 = PWM_IR_PWMMRn(4), /**< Interrupt flag for PWM match channel 4 */
+ PWM_INTSTAT_MR6 = PWM_IR_PWMMRn(5), /**< Interrupt flag for PWM match channel 5 */
+ PWM_INTSTAT_MR5 = PWM_IR_PWMMRn(6), /**< Interrupt flag for PWM match channel 6 */
+}PWM_INTSTAT_TYPE;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup PWM_Public_Functions PWM Public Functions
+ * @{
+ */
+
+void PWM_PinConfig(LPC_PWM_TypeDef *PWMx, uint8_t PWM_Channel, uint8_t PinselOption);
+IntStatus PWM_GetIntStatus(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag);
+void PWM_ClearIntPending(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag);
+void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct);
+void PWM_Init(LPC_PWM_TypeDef *PWMx, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct);
+void PWM_DeInit (LPC_PWM_TypeDef *PWMx);
+void PWM_Cmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState);
+void PWM_CounterCmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState);
+void PWM_ResetCounter(LPC_PWM_TypeDef *PWMx);
+void PWM_ConfigMatch(LPC_PWM_TypeDef *PWMx, PWM_MATCHCFG_Type *PWM_MatchConfigStruct);
+void PWM_ConfigCapture(LPC_PWM_TypeDef *PWMx, PWM_CAPTURECFG_Type *PWM_CaptureConfigStruct);
+uint32_t PWM_GetCaptureValue(LPC_PWM_TypeDef *PWMx, uint8_t CaptureChannel);
+void PWM_MatchUpdate(LPC_PWM_TypeDef *PWMx, uint8_t MatchChannel, \
+ uint32_t MatchValue, uint8_t UpdateType);
+void PWM_ChannelConfig(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, uint8_t ModeOption);
+void PWM_ChannelCmd(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, FunctionalState NewState);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_PWM_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_qei.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_qei.h new file mode 100644 index 0000000..7b578c9 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_qei.h @@ -0,0 +1,412 @@ +/***********************************************************************//**
+ * @file lpc17xx_qei.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for QEI firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup QEI QEI
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_QEI_H_
+#define LPC17XX_QEI_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup QEI_Public_Macros QEI Public Macros
+ * @{
+ */
+
+/* QEI Reset types */
+#define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
+#define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
+#define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
+#define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
+
+/* QEI Direction Invert Type Option */
+#define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
+#define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
+
+/* QEI Signal Mode Option */
+#define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
+#define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
+
+/* QEI Capture Mode Option */
+#define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
+#define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
+
+/* QEI Invert Index Signal Option */
+#define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
+#define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
+
+/* QEI timer reload option */
+#define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
+#define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
+
+/* QEI Flag Status type */
+#define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
+
+/* QEI Compare Position channel option */
+#define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
+#define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
+#define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
+
+/* QEI interrupt flag type */
+#define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
+#define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
+#define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
+#define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
+#define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
+#define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
+#define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
+ current position interrupt */
+#define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
+ current position interrupt */
+#define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
+ current position interrupt */
+#define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
+ index count interrupt */
+#define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
+#define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
+#define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup QEI_Private_Macros QEI Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/* Quadrature Encoder Interface Control Register Definition --------------------- */
+/*********************************************************************//**
+ * Macro defines for QEI Control register
+ **********************************************************************/
+#define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
+#define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
+#define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
+#define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
+#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Configuration register
+ **********************************************************************/
+#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
+#define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
+#define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
+#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
+#define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Status register
+ **********************************************************************/
+#define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
+#define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
+
+/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Status register
+ **********************************************************************/
+#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
+#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
+#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
+#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
+#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
+#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
+#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
+ both the POS0_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
+ both the POS1_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
+ both the POS2_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Set register
+ **********************************************************************/
+#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
+#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
+#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
+#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
+#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Clear register
+ **********************************************************************/
+#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
+#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
+#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
+#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
+#define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Enable register
+ **********************************************************************/
+#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
+#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Enable Set register
+ **********************************************************************/
+#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
+#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Enable Clear register
+ **********************************************************************/
+#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
+#define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macro check QEI peripheral */
+#define PARAM_QEIx(n) ((n==LPC_QEI))
+
+/* Macro check QEI reset type */
+#define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \
+|| (n==QEI_RESET_POSOnIDX) \
+|| (n==QEI_RESET_VEL) \
+|| (n==QEI_RESET_IDX))
+
+/* Macro check QEI Direction invert mode */
+#define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))
+
+/* Macro check QEI signal mode */
+#define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))
+
+/* Macro check QEI Capture mode */
+#define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))
+
+/* Macro check QEI Invert index mode */
+#define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))
+
+/* Macro check QEI Direction invert mode */
+#define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))
+
+/* Macro check QEI status type */
+#define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR))
+
+/* Macro check QEI combine position type */
+#define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))
+
+/* Macro check QEI interrupt flag type */
+#define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \
+|| (n==QEI_INTFLAG_TIM_Int) \
+|| (n==QEI_INTFLAG_VELC_Int) \
+|| (n==QEI_INTFLAG_DIR_Int) \
+|| (n==QEI_INTFLAG_ERR_Int) \
+|| (n==QEI_INTFLAG_ENCLK_Int) \
+|| (n==QEI_INTFLAG_POS0_Int) \
+|| (n==QEI_INTFLAG_POS1_Int) \
+|| (n==QEI_INTFLAG_POS2_Int) \
+|| (n==QEI_INTFLAG_REV_Int) \
+|| (n==QEI_INTFLAG_POS0REV_Int) \
+|| (n==QEI_INTFLAG_POS1REV_Int) \
+|| (n==QEI_INTFLAG_POS2REV_Int))
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup QEI_Public_Types QEI Public Types
+ * @{
+ */
+
+/**
+ * @brief QEI Configuration structure type definition
+ */
+typedef struct {
+ uint32_t DirectionInvert :1; /**< Direction invert option:
+ - QEI_DIRINV_NONE: QEI Direction is normal
+ - QEI_DIRINV_CMPL: QEI Direction is complemented
+ */
+ uint32_t SignalMode :1; /**< Signal mode Option:
+ - QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
+ - QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
+ */
+ uint32_t CaptureMode :1; /**< Capture Mode Option:
+ - QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
+ - QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
+ */
+ uint32_t InvertIndex :1; /**< Invert Index Option:
+ - QEI_INVINX_NONE: the sense of the index input is normal
+ - QEI_INVINX_EN: inverts the sense of the index input
+ */
+} QEI_CFG_Type;
+
+/**
+ * @brief Timer Reload Configuration structure type definition
+ */
+typedef struct {
+
+ uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be:
+ - QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
+ - QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
+ */
+ uint8_t Reserved[3];
+ uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched
+ with Velocity Timer Reload Option
+ */
+} QEI_RELOADCFG_Type;
+
+/**
+ * @}
+ */
+
+
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup QEI_Public_Functions QEI Public Functions
+ * @{
+ */
+
+void QEI_Reset(LPC_QEI_TypeDef *QEIx, uint32_t ulResetType);
+void QEI_Init(LPC_QEI_TypeDef *QEIx, QEI_CFG_Type *QEI_ConfigStruct);
+void QEI_ConfigStructInit(QEI_CFG_Type *QIE_InitStruct);
+void QEI_DeInit(LPC_QEI_TypeDef *QEIx);
+FlagStatus QEI_GetStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulFlagType);
+uint32_t QEI_GetPosition(LPC_QEI_TypeDef *QEIx);
+void QEI_SetMaxPosition(LPC_QEI_TypeDef *QEIx, uint32_t ulMaxPos);
+void QEI_SetPositionComp(LPC_QEI_TypeDef *QEIx, uint8_t bPosCompCh, uint32_t ulPosComp);
+uint32_t QEI_GetIndex(LPC_QEI_TypeDef *QEIx);
+void QEI_SetIndexComp(LPC_QEI_TypeDef *QEIx, uint32_t ulIndexComp);
+void QEI_SetTimerReload(LPC_QEI_TypeDef *QEIx, QEI_RELOADCFG_Type *QEIReloadStruct);
+uint32_t QEI_GetTimer(LPC_QEI_TypeDef *QEIx);
+uint32_t QEI_GetVelocity(LPC_QEI_TypeDef *QEIx);
+uint32_t QEI_GetVelocityCap(LPC_QEI_TypeDef *QEIx);
+void QEI_SetVelocityComp(LPC_QEI_TypeDef *QEIx, uint32_t ulVelComp);
+void QEI_SetDigiFilter(LPC_QEI_TypeDef *QEIx, uint32_t ulSamplingPulse);
+FlagStatus QEI_GetIntStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
+void QEI_IntCmd(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType, FunctionalState NewState);
+void QEI_IntSet(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
+void QEI_IntClear(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
+uint32_t QEI_CalculateRPM(LPC_QEI_TypeDef *QEIx, uint32_t ulVelCapValue, uint32_t ulPPR);
+
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_QEI_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_rit.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_rit.h new file mode 100644 index 0000000..9d2e515 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_rit.h @@ -0,0 +1,100 @@ +/***********************************************************************//**
+ * @file lpc17xx_rit.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for RIT firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup RIT RIT
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_RIT_H_
+#define LPC17XX_RIT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup RIT_Private_Macros RIT Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for RIT control register
+ **********************************************************************/
+/** Set interrupt flag when the counter value equals the masked compare value */
+#define RIT_CTRL_INTEN ((uint32_t) (1))
+/** Set timer enable clear to 0 when the counter value equals the masked compare value */
+#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))
+/** Set timer enable on debug */
+#define RIT_CTRL_ENBR ((uint32_t) _BIT(2))
+/** Set timer enable */
+#define RIT_CTRL_TEN ((uint32_t) _BIT(3))
+
+/** Macro to determine if it is valid RIT peripheral */
+#define PARAM_RITx(n) (((uint32_t *)n)==((uint32_t *)LPC_RIT))
+/**
+ * @}
+ */
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup RIT_Public_Functions RIT Public Functions
+ * @{
+ */
+/* RIT Init/DeInit functions */
+void RIT_Init(LPC_RIT_TypeDef *RITx);
+void RIT_DeInit(LPC_RIT_TypeDef *RITx);
+
+/* RIT config timer functions */
+void RIT_TimerConfig(LPC_RIT_TypeDef *RITx, uint32_t time_interval);
+
+/* Enable/Disable RIT functions */
+void RIT_TimerClearCmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState);
+void RIT_Cmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState);
+void RIT_TimerDebugCmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState);
+
+/* RIT Interrupt functions */
+IntStatus RIT_GetIntStatus(LPC_RIT_TypeDef *RITx);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_RIT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_rtc.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_rtc.h new file mode 100644 index 0000000..2f12d6f --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_rtc.h @@ -0,0 +1,302 @@ +/***********************************************************************//**
+ * @file lpc17xx_rtc.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for RTC firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup RTC RTC
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_RTC_H_
+#define LPC17XX_RTC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/* ----------------------- BIT DEFINITIONS ----------------------------------- */
+/* Miscellaneous register group --------------------------------------------- */
+/**********************************************************************
+* ILR register definitions
+**********************************************************************/
+/** ILR register mask */
+#define RTC_ILR_BITMASK ((0x00000003))
+/** Bit inform the source interrupt is counter increment*/
+#define RTC_IRL_RTCCIF ((1<<0))
+/** Bit inform the source interrupt is alarm match*/
+#define RTC_IRL_RTCALF ((1<<1))
+
+/**********************************************************************
+* CCR register definitions
+**********************************************************************/
+/** CCR register mask */
+#define RTC_CCR_BITMASK ((0x00000013))
+/** Clock enable */
+#define RTC_CCR_CLKEN ((1<<0))
+/** Clock reset */
+#define RTC_CCR_CTCRST ((1<<1))
+/** Calibration counter enable */
+#define RTC_CCR_CCALEN ((1<<4))
+
+/**********************************************************************
+* CIIR register definitions
+**********************************************************************/
+/** Counter Increment Interrupt bit for second */
+#define RTC_CIIR_IMSEC ((1<<0))
+/** Counter Increment Interrupt bit for minute */
+#define RTC_CIIR_IMMIN ((1<<1))
+/** Counter Increment Interrupt bit for hour */
+#define RTC_CIIR_IMHOUR ((1<<2))
+/** Counter Increment Interrupt bit for day of month */
+#define RTC_CIIR_IMDOM ((1<<3))
+/** Counter Increment Interrupt bit for day of week */
+#define RTC_CIIR_IMDOW ((1<<4))
+/** Counter Increment Interrupt bit for day of year */
+#define RTC_CIIR_IMDOY ((1<<5))
+/** Counter Increment Interrupt bit for month */
+#define RTC_CIIR_IMMON ((1<<6))
+/** Counter Increment Interrupt bit for year */
+#define RTC_CIIR_IMYEAR ((1<<7))
+/** CIIR bit mask */
+#define RTC_CIIR_BITMASK ((0xFF))
+
+/**********************************************************************
+* AMR register definitions
+**********************************************************************/
+/** Counter Increment Select Mask bit for second */
+#define RTC_AMR_AMRSEC ((1<<0))
+/** Counter Increment Select Mask bit for minute */
+#define RTC_AMR_AMRMIN ((1<<1))
+/** Counter Increment Select Mask bit for hour */
+#define RTC_AMR_AMRHOUR ((1<<2))
+/** Counter Increment Select Mask bit for day of month */
+#define RTC_AMR_AMRDOM ((1<<3))
+/** Counter Increment Select Mask bit for day of week */
+#define RTC_AMR_AMRDOW ((1<<4))
+/** Counter Increment Select Mask bit for day of year */
+#define RTC_AMR_AMRDOY ((1<<5))
+/** Counter Increment Select Mask bit for month */
+#define RTC_AMR_AMRMON ((1<<6))
+/** Counter Increment Select Mask bit for year */
+#define RTC_AMR_AMRYEAR ((1<<7))
+/** AMR bit mask */
+#define RTC_AMR_BITMASK ((0xFF))
+
+/**********************************************************************
+* RTC_AUX register definitions
+**********************************************************************/
+/** RTC Oscillator Fail detect flag */
+#define RTC_AUX_RTC_OSCF ((1<<4))
+
+/**********************************************************************
+* RTC_AUXEN register definitions
+**********************************************************************/
+/** Oscillator Fail Detect interrupt enable*/
+#define RTC_AUXEN_RTC_OSCFEN ((1<<4))
+
+/* Consolidated time register group ----------------------------------- */
+/**********************************************************************
+* Consolidated Time Register 0 definitions
+**********************************************************************/
+#define RTC_CTIME0_SECONDS_MASK ((0x3F))
+#define RTC_CTIME0_MINUTES_MASK ((0x3F00))
+#define RTC_CTIME0_HOURS_MASK ((0x1F0000))
+#define RTC_CTIME0_DOW_MASK ((0x7000000))
+
+/**********************************************************************
+* Consolidated Time Register 1 definitions
+**********************************************************************/
+#define RTC_CTIME1_DOM_MASK ((0x1F))
+#define RTC_CTIME1_MONTH_MASK ((0xF00))
+#define RTC_CTIME1_YEAR_MASK ((0xFFF0000))
+
+/**********************************************************************
+* Consolidated Time Register 2 definitions
+**********************************************************************/
+#define RTC_CTIME2_DOY_MASK ((0xFFF))
+
+/**********************************************************************
+* Time Counter Group and Alarm register group
+**********************************************************************/
+/** SEC register mask */
+#define RTC_SEC_MASK (0x0000003F)
+/** MIN register mask */
+#define RTC_MIN_MASK (0x0000003F)
+/** HOUR register mask */
+#define RTC_HOUR_MASK (0x0000001F)
+/** DOM register mask */
+#define RTC_DOM_MASK (0x0000001F)
+/** DOW register mask */
+#define RTC_DOW_MASK (0x00000007)
+/** DOY register mask */
+#define RTC_DOY_MASK (0x000001FF)
+/** MONTH register mask */
+#define RTC_MONTH_MASK (0x0000000F)
+/** YEAR register mask */
+#define RTC_YEAR_MASK (0x00000FFF)
+
+#define RTC_SECOND_MAX 59 /*!< Maximum value of second */
+#define RTC_MINUTE_MAX 59 /*!< Maximum value of minute*/
+#define RTC_HOUR_MAX 23 /*!< Maximum value of hour*/
+#define RTC_MONTH_MIN 1 /*!< Minimum value of month*/
+#define RTC_MONTH_MAX 12 /*!< Maximum value of month*/
+#define RTC_DAYOFMONTH_MIN 1 /*!< Minimum value of day of month*/
+#define RTC_DAYOFMONTH_MAX 31 /*!< Maximum value of day of month*/
+#define RTC_DAYOFWEEK_MAX 6 /*!< Maximum value of day of week*/
+#define RTC_DAYOFYEAR_MIN 1 /*!< Minimum value of day of year*/
+#define RTC_DAYOFYEAR_MAX 366 /*!< Maximum value of day of year*/
+#define RTC_YEAR_MAX 4095 /*!< Maximum value of year*/
+
+/**********************************************************************
+* Calibration register
+**********************************************************************/
+/* Calibration register */
+/** Calibration value */
+#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))
+/** Calibration direction */
+#define RTC_CALIBRATION_LIBDIR ((1<<17))
+/** Calibration max value */
+#define RTC_CALIBRATION_MAX ((0x20000))
+/** Calibration definitions */
+#define RTC_CALIB_DIR_FORWARD ((uint8_t)(0))
+#define RTC_CALIB_DIR_BACKWARD ((uint8_t)(1))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid RTC peripheral */
+#define PARAM_RTCx(x) (((uint32_t *)x)==((uint32_t *)LPC_RTC))
+
+/* Macro check RTC interrupt type */
+#define PARAM_RTC_INT(n) ((n==RTC_INT_COUNTER_INCREASE) || (n==RTC_INT_ALARM))
+
+/* Macro check RTC time type */
+#define PARAM_RTC_TIMETYPE(n) ((n==RTC_TIMETYPE_SECOND) || (n==RTC_TIMETYPE_MINUTE) \
+|| (n==RTC_TIMETYPE_HOUR) || (n==RTC_TIMETYPE_DAYOFWEEK) \
+|| (n==RTC_TIMETYPE_DAYOFMONTH) || (n==RTC_TIMETYPE_DAYOFYEAR) \
+|| (n==RTC_TIMETYPE_MONTH) || (n==RTC_TIMETYPE_YEAR))
+
+/* Macro check RTC calibration type */
+#define PARAM_RTC_CALIB_DIR(n) ((n==RTC_CALIB_DIR_FORWARD) || (n==RTC_CALIB_DIR_BACKWARD))
+
+/* Macro check RTC GPREG type */
+#define PARAM_RTC_GPREG_CH(n) ((n>=0) && (n<=4))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup RTC_Public_Types RTC Public Types
+ * @{
+ */
+
+/** @brief Time structure definitions for easy manipulate the data */
+typedef struct {
+ uint32_t SEC; /*!< Seconds Register */
+ uint32_t MIN; /*!< Minutes Register */
+ uint32_t HOUR; /*!< Hours Register */
+ uint32_t DOM; /*!< Day of Month Register */
+ uint32_t DOW; /*!< Day of Week Register */
+ uint32_t DOY; /*!< Day of Year Register */
+ uint32_t MONTH; /*!< Months Register */
+ uint32_t YEAR; /*!< Years Register */
+} RTC_TIME_Type;
+
+/** @brief RTC interrupt source */
+typedef enum {
+ RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */
+ RTC_INT_ALARM = RTC_IRL_RTCALF, /*!< The alarm interrupt */
+} RTC_INT_OPT;
+
+
+/** @brief RTC time type option */
+typedef enum {
+ RTC_TIMETYPE_SECOND = 0, /*!< Second */
+ RTC_TIMETYPE_MINUTE = 1, /*!< Month */
+ RTC_TIMETYPE_HOUR = 2, /*!< Hour */
+ RTC_TIMETYPE_DAYOFWEEK = 3, /*!< Day of week */
+ RTC_TIMETYPE_DAYOFMONTH = 4, /*!< Day of month */
+ RTC_TIMETYPE_DAYOFYEAR = 5, /*!< Day of year */
+ RTC_TIMETYPE_MONTH = 6, /*!< Month */
+ RTC_TIMETYPE_YEAR = 7, /*!< Year */
+} RTC_TIMETYPE_Num;
+
+/**
+ * @}
+ */
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup RTC_Public_Functions RTC Public Functions
+ * @{
+ */
+
+void RTC_Init (LPC_RTC_TypeDef *RTCx);
+void RTC_DeInit(LPC_RTC_TypeDef *RTCx);
+void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx);
+void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
+void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \
+ FunctionalState NewState);
+void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \
+ FunctionalState NewState);
+void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue);
+uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
+void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
+void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
+void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue);
+uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
+void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
+void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
+IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
+void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
+void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
+void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir);
+void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value);
+uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_RTC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_spi.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_spi.h new file mode 100644 index 0000000..21d2e21 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_spi.h @@ -0,0 +1,316 @@ +/***********************************************************************//**
+ * @file lpc17xx_spi.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for SPI firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SPI SPI
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_SPI_H_
+#define LPC17XX_SPI_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup SPI_Public_Macros SPI Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * SPI configuration parameter defines
+ **********************************************************************/
+/** Clock phase control bit */
+#define SPI_CPHA_FIRST ((uint32_t)(0))
+#define SPI_CPHA_SECOND ((uint32_t)(1<<3))
+
+/** Clock polarity control bit */
+#define SPI_CPOL_HI ((uint32_t)(0))
+#define SPI_CPOL_LO ((uint32_t)(1<<4))
+
+/** SPI master mode enable */
+#define SPI_SLAVE_MODE ((uint32_t)(0))
+#define SPI_MASTER_MODE ((uint32_t)(1<<5))
+
+/** LSB enable bit */
+#define SPI_DATA_MSB_FIRST ((uint32_t)(0))
+#define SPI_DATA_LSB_FIRST ((uint32_t)(1<<6))
+
+/** SPI data bit number defines */
+#define SPI_DATABIT_16 SPI_SPCR_BITS(0) /*!< Databit number = 16 */
+#define SPI_DATABIT_8 SPI_SPCR_BITS(0x08) /*!< Databit number = 8 */
+#define SPI_DATABIT_9 SPI_SPCR_BITS(0x09) /*!< Databit number = 9 */
+#define SPI_DATABIT_10 SPI_SPCR_BITS(0x0A) /*!< Databit number = 10 */
+#define SPI_DATABIT_11 SPI_SPCR_BITS(0x0B) /*!< Databit number = 11 */
+#define SPI_DATABIT_12 SPI_SPCR_BITS(0x0C) /*!< Databit number = 12 */
+#define SPI_DATABIT_13 SPI_SPCR_BITS(0x0D) /*!< Databit number = 13 */
+#define SPI_DATABIT_14 SPI_SPCR_BITS(0x0E) /*!< Databit number = 14 */
+#define SPI_DATABIT_15 SPI_SPCR_BITS(0x0F) /*!< Databit number = 15 */
+
+/*********************************************************************//**
+ * SPI Status Flag defines
+ **********************************************************************/
+/** Slave abort */
+#define SPI_STAT_ABRT SPI_SPSR_ABRT
+/** Mode fault */
+#define SPI_STAT_MODF SPI_SPSR_MODF
+/** Read overrun */
+#define SPI_STAT_ROVR SPI_SPSR_ROVR
+/** Write collision */
+#define SPI_STAT_WCOL SPI_SPSR_WCOL
+/** SPI transfer complete flag */
+#define SPI_STAT_SPIF SPI_SPSR_SPIF
+
+/* SPI Status Implementation definitions */
+#define SPI_STAT_DONE (1UL<<8) /**< Done */
+#define SPI_STAT_ERROR (1UL<<9) /**< Error */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for SPI Control Register
+ **********************************************************************/
+/** Bit enable, the SPI controller sends and receives the number
+ * of bits selected by bits 11:8 */
+#define SPI_SPCR_BIT_EN ((uint32_t)(1<<2))
+/** Clock phase control bit */
+#define SPI_SPCR_CPHA_SECOND ((uint32_t)(1<<3))
+/** Clock polarity control bit */
+#define SPI_SPCR_CPOL_LOW ((uint32_t)(1<<4))
+/** SPI master mode enable */
+#define SPI_SPCR_MSTR ((uint32_t)(1<<5))
+/** LSB enable bit */
+#define SPI_SPCR_LSBF ((uint32_t)(1<<6))
+/** SPI interrupt enable bit */
+#define SPI_SPCR_SPIE ((uint32_t)(1<<7))
+/** When bit 2 of this register is 1, this field controls the
+number of bits per transfer */
+#define SPI_SPCR_BITS(n) ((n==0) ? ((uint32_t)0) : ((uint32_t)((n&0x0F)<<8)))
+/** SPI Control bit mask */
+#define SPI_SPCR_BITMASK ((uint32_t)(0xFFC))
+
+/*********************************************************************//**
+ * Macro defines for SPI Status Register
+ **********************************************************************/
+/** Slave abort */
+#define SPI_SPSR_ABRT ((uint32_t)(1<<3))
+/** Mode fault */
+#define SPI_SPSR_MODF ((uint32_t)(1<<4))
+/** Read overrun */
+#define SPI_SPSR_ROVR ((uint32_t)(1<<5))
+/** Write collision */
+#define SPI_SPSR_WCOL ((uint32_t)(1<<6))
+/** SPI transfer complete flag */
+#define SPI_SPSR_SPIF ((uint32_t)(1<<7))
+/** SPI Status bit mask */
+#define SPI_SPSR_BITMASK ((uint32_t)(0xF8))
+
+/*********************************************************************//**
+ * Macro defines for SPI Data Register
+ **********************************************************************/
+/** SPI Data low bit-mask */
+#define SPI_SPDR_LO_MASK ((uint32_t)(0xFF))
+/** SPI Data high bit-mask */
+#define SPI_SPDR_HI_MASK ((uint32_t)(0xFF00))
+/** SPI Data bit-mask */
+#define SPI_SPDR_BITMASK ((uint32_t)(0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for SPI Clock Counter Register
+ **********************************************************************/
+/** SPI clock counter setting */
+#define SPI_SPCCR_COUNTER(n) ((uint32_t)(n&0xFF))
+/** SPI clock counter bit-mask */
+#define SPI_SPCCR_BITMASK ((uint32_t)(0xFF))
+
+/***********************************************************************
+ * Macro defines for SPI Test Control Register
+ **********************************************************************/
+/** SPI Test bit */
+#define SPI_SPTCR_TEST_MASK ((uint32_t)(0xFE))
+/** SPI Test register bit mask */
+#define SPI_SPTCR_BITMASK ((uint32_t)(0xFE))
+
+/*********************************************************************//**
+ * Macro defines for SPI Test Status Register
+ **********************************************************************/
+/** Slave abort */
+#define SPI_SPTSR_ABRT ((uint32_t)(1<<3))
+/** Mode fault */
+#define SPI_SPTSR_MODF ((uint32_t)(1<<4))
+/** Read overrun */
+#define SPI_SPTSR_ROVR ((uint32_t)(1<<5))
+/** Write collision */
+#define SPI_SPTSR_WCOL ((uint32_t)(1<<6))
+/** SPI transfer complete flag */
+#define SPI_SPTSR_SPIF ((uint32_t)(1<<7))
+/** SPI Status bit mask */
+#define SPI_SPTSR_MASKBIT ((uint32_t)(0xF8))
+
+/*********************************************************************//**
+ * Macro defines for SPI Interrupt Register
+ **********************************************************************/
+/** SPI interrupt flag */
+#define SPI_SPINT_INTFLAG ((uint32_t)(1<<0))
+/** SPI interrupt register bit mask */
+#define SPI_SPINT_BITMASK ((uint32_t)(0x01))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid SPI port number */
+#define PARAM_SPIx(n) (((uint32_t *)n)==((uint32_t *)LPC_SPI))
+
+/** Macro check Clock phase control mode */
+#define PARAM_SPI_CPHA(n) ((n==SPI_CPHA_FIRST) || (n==SPI_CPHA_SECOND))
+
+/** Macro check Clock polarity control mode */
+#define PARAM_SPI_CPOL(n) ((n==SPI_CPOL_HI) || (n==SPI_CPOL_LO))
+
+/** Macro check master/slave mode */
+#define PARAM_SPI_MODE(n) ((n==SPI_SLAVE_MODE) || (n==SPI_MASTER_MODE))
+
+/** Macro check LSB/MSB mode */
+#define PARAM_SPI_DATA_ORDER(n) ((n==SPI_DATA_MSB_FIRST) || (n==SPI_DATA_LSB_FIRST))
+
+/** Macro check databit value */
+#define PARAM_SPI_DATABIT(n) ((n==SPI_DATABIT_16) || (n==SPI_DATABIT_8) \
+|| (n==SPI_DATABIT_9) || (n==SPI_DATABIT_10) \
+|| (n==SPI_DATABIT_11) || (n==SPI_DATABIT_12) \
+|| (n==SPI_DATABIT_13) || (n==SPI_DATABIT_14) \
+|| (n==SPI_DATABIT_15))
+
+/** Macro check status flag */
+#define PARAM_SPI_STAT(n) ((n==SPI_STAT_ABRT) || (n==SPI_STAT_MODF) \
+|| (n==SPI_STAT_ROVR) || (n==SPI_STAT_WCOL) \
+|| (n==SPI_STAT_SPIF))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup SPI_Public_Types SPI Public Types
+ * @{
+ */
+
+/** @brief SPI configuration structure */
+typedef struct {
+ uint32_t Databit; /** Databit number, should be SPI_DATABIT_x,
+ where x is in range from 8 - 16 */
+ uint32_t CPHA; /** Clock phase, should be:
+ - SPI_CPHA_FIRST: first clock edge
+ - SPI_CPHA_SECOND: second clock edge */
+ uint32_t CPOL; /** Clock polarity, should be:
+ - SPI_CPOL_HI: high level
+ - SPI_CPOL_LO: low level */
+ uint32_t Mode; /** SPI mode, should be:
+ - SPI_MASTER_MODE: Master mode
+ - SPI_SLAVE_MODE: Slave mode */
+ uint32_t DataOrder; /** Data order, should be:
+ - SPI_DATA_MSB_FIRST: MSB first
+ - SPI_DATA_LSB_FIRST: LSB first */
+ uint32_t ClockRate; /** Clock rate,in Hz, should not exceed
+ (SPI peripheral clock)/8 */
+} SPI_CFG_Type;
+
+
+/**
+ * @brief SPI Transfer Type definitions
+ */
+typedef enum {
+ SPI_TRANSFER_POLLING = 0, /**< Polling transfer */
+ SPI_TRANSFER_INTERRUPT /**< Interrupt transfer */
+} SPI_TRANSFER_Type;
+
+/**
+ * @brief SPI Data configuration structure definitions
+ */
+typedef struct {
+ void *tx_data; /**< Pointer to transmit data */
+ void *rx_data; /**< Pointer to transmit data */
+ uint32_t length; /**< Length of transfer data */
+ uint32_t counter; /**< Data counter index */
+ uint32_t status; /**< Current status of SPI activity */
+} SPI_DATA_SETUP_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SPI_Public_Functions SPI Public Functions
+ * @{
+ */
+
+/* SPI Init/DeInit functions ---------*/
+void SPI_Init(LPC_SPI_TypeDef *SPIx, SPI_CFG_Type *SPI_ConfigStruct);
+void SPI_DeInit(LPC_SPI_TypeDef *SPIx);
+void SPI_SetClock (LPC_SPI_TypeDef *SPIx, uint32_t target_clock);
+void SPI_ConfigStructInit(SPI_CFG_Type *SPI_InitStruct);
+
+/* SPI transfer functions ------------*/
+void SPI_SendData(LPC_SPI_TypeDef *SPIx, uint16_t Data);
+uint16_t SPI_ReceiveData(LPC_SPI_TypeDef *SPIx);
+int32_t SPI_ReadWrite (LPC_SPI_TypeDef *SPIx, SPI_DATA_SETUP_Type *dataCfg, SPI_TRANSFER_Type xfType);
+
+/* SPI Interrupt functions ---------*/
+void SPI_IntCmd(LPC_SPI_TypeDef *SPIx, FunctionalState NewState);
+IntStatus SPI_GetIntStatus (LPC_SPI_TypeDef *SPIx);
+void SPI_ClearIntPending(LPC_SPI_TypeDef *SPIx);
+
+/* SPI get information functions-----*/
+uint8_t SPI_GetDataSize (LPC_SPI_TypeDef *SPIx);
+uint32_t SPI_GetStatus(LPC_SPI_TypeDef *SPIx);
+FlagStatus SPI_CheckStatus (uint32_t inputSPIStatus, uint8_t SPIStatus);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_SPI_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_ssp.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_ssp.h new file mode 100644 index 0000000..0a1cf87 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_ssp.h @@ -0,0 +1,460 @@ +/***********************************************************************//**
+ * @file lpc17xx_ssp.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for SSP firmware library on LPC17xx
+ * @version 3.0
+ * @date 18. June. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SSP SSP
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_SSP_H_
+#define LPC17XX_SSP_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup SSP_Public_Macros SSP Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * SSP configuration parameter defines
+ **********************************************************************/
+/** Clock phase control bit */
+#define SSP_CPHA_FIRST ((uint32_t)(0))
+#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
+
+
+/** Clock polarity control bit */
+/* There's no bug here!!!
+ * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
+ * That means the active clock is in HI state.
+ * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
+ * high between frames. That means the active clock is in LO state.
+ */
+#define SSP_CPOL_HI ((uint32_t)(0))
+#define SSP_CPOL_LO SSP_CR0_CPOL_HI
+
+/** SSP master mode enable */
+#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
+#define SSP_MASTER_MODE ((uint32_t)(0))
+
+/** SSP data bit number defines */
+#define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
+#define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
+#define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
+#define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
+#define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
+#define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
+#define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
+#define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
+#define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
+#define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
+#define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
+#define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
+#define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
+
+/** SSP Frame Format definition */
+/** Motorola SPI mode */
+#define SSP_FRAME_SPI SSP_CR0_FRF_SPI
+/** TI synchronous serial mode */
+#define SSP_FRAME_TI SSP_CR0_FRF_TI
+/** National Micro-wire mode */
+#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
+
+/*********************************************************************//**
+ * SSP Status defines
+ **********************************************************************/
+/** SSP status TX FIFO Empty bit */
+#define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
+/** SSP status TX FIFO not full bit */
+#define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
+/** SSP status RX FIFO not empty bit */
+#define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
+/** SSP status RX FIFO full bit */
+#define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
+/** SSP status SSP Busy bit */
+#define SSP_STAT_BUSY SSP_SR_BSY
+
+/*********************************************************************//**
+ * SSP Interrupt Configuration defines
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_INTCFG_ROR SSP_IMSC_ROR
+/** Receive TimeOut */
+#define SSP_INTCFG_RT SSP_IMSC_RT
+/** Rx FIFO is at least half full */
+#define SSP_INTCFG_RX SSP_IMSC_RX
+/** Tx FIFO is at least half empty */
+#define SSP_INTCFG_TX SSP_IMSC_TX
+
+/*********************************************************************//**
+ * SSP Configured Interrupt Status defines
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_INTSTAT_ROR SSP_MIS_ROR
+/** Receive TimeOut */
+#define SSP_INTSTAT_RT SSP_MIS_RT
+/** Rx FIFO is at least half full */
+#define SSP_INTSTAT_RX SSP_MIS_RX
+/** Tx FIFO is at least half empty */
+#define SSP_INTSTAT_TX SSP_MIS_TX
+
+/*********************************************************************//**
+ * SSP Raw Interrupt Status defines
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
+/** Receive TimeOut */
+#define SSP_INTSTAT_RAW_RT SSP_RIS_RT
+/** Rx FIFO is at least half full */
+#define SSP_INTSTAT_RAW_RX SSP_RIS_RX
+/** Tx FIFO is at least half empty */
+#define SSP_INTSTAT_RAW_TX SSP_RIS_TX
+
+/*********************************************************************//**
+ * SSP Interrupt Clear defines
+ **********************************************************************/
+/** Writing a 1 to this bit clears the "frame was received when
+ * RxFIFO was full" interrupt */
+#define SSP_INTCLR_ROR SSP_ICR_ROR
+/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
+ * has not been read for a timeout period" interrupt */
+#define SSP_INTCLR_RT SSP_ICR_RT
+
+/*********************************************************************//**
+ * SSP DMA defines
+ **********************************************************************/
+/** SSP bit for enabling RX DMA */
+#define SSP_DMA_RX SSP_DMA_RXDMA_EN
+/** SSP bit for enabling TX DMA */
+#define SSP_DMA_TX SSP_DMA_TXDMA_EN
+
+/* SSP Status Implementation definitions */
+#define SSP_STAT_DONE (1UL<<8) /**< Done */
+#define SSP_STAT_ERROR (1UL<<9) /**< Error */
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup SSP_Private_Macros SSP Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for CR0 register
+ **********************************************************************/
+/** SSP data size select, must be 4 bits to 16 bits */
+#define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
+/** SSP control 0 Motorola SPI mode */
+#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
+/** SSP control 0 TI synchronous serial mode */
+#define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
+/** SSP control 0 National Micro-wire mode */
+#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
+/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
+ bus clock high between frames, (0) = low */
+#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
+/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
+ on the second clock transition of the frame, (0) = first */
+#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
+/** SSP serial clock rate value load macro, divider rate is
+ PERIPH_CLK / (cpsr * (SCR + 1)) */
+#define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
+/** SSP CR0 bit mask */
+#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for CR1 register
+ **********************************************************************/
+/** SSP control 1 loopback mode enable bit */
+#define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
+/** SSP control 1 enable bit */
+#define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
+/** SSP control 1 slave enable */
+#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
+/** SSP control 1 slave out disable bit, disables transmit line in slave
+ mode */
+#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
+/** SSP CR1 bit mask */
+#define SSP_CR1_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for DR register
+ **********************************************************************/
+/** SSP data bit mask */
+#define SSP_DR_BITMASK(n) ((n)&0xFFFF)
+
+/*********************************************************************//**
+ * Macro defines for SR register
+ **********************************************************************/
+/** SSP status TX FIFO Empty bit */
+#define SSP_SR_TFE ((uint32_t)(1<<0))
+/** SSP status TX FIFO not full bit */
+#define SSP_SR_TNF ((uint32_t)(1<<1))
+/** SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE ((uint32_t)(1<<2))
+/** SSP status RX FIFO full bit */
+#define SSP_SR_RFF ((uint32_t)(1<<3))
+/** SSP status SSP Busy bit */
+#define SSP_SR_BSY ((uint32_t)(1<<4))
+/** SSP SR bit mask */
+#define SSP_SR_BITMASK ((uint32_t)(0x1F))
+
+/*********************************************************************//**
+ * Macro defines for CPSR register
+ **********************************************************************/
+/** SSP clock prescaler */
+#define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
+/** SSP CPSR bit mask */
+#define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro define for (IMSC) Interrupt Mask Set/Clear registers
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_IMSC_ROR ((uint32_t)(1<<0))
+/** Receive TimeOut */
+#define SSP_IMSC_RT ((uint32_t)(1<<1))
+/** Rx FIFO is at least half full */
+#define SSP_IMSC_RX ((uint32_t)(1<<2))
+/** Tx FIFO is at least half empty */
+#define SSP_IMSC_TX ((uint32_t)(1<<3))
+/** IMSC bit mask */
+#define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro define for (RIS) Raw Interrupt Status registers
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_RIS_ROR ((uint32_t)(1<<0))
+/** Receive TimeOut */
+#define SSP_RIS_RT ((uint32_t)(1<<1))
+/** Rx FIFO is at least half full */
+#define SSP_RIS_RX ((uint32_t)(1<<2))
+/** Tx FIFO is at least half empty */
+#define SSP_RIS_TX ((uint32_t)(1<<3))
+/** RIS bit mask */
+#define SSP_RIS_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro define for (MIS) Masked Interrupt Status registers
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_MIS_ROR ((uint32_t)(1<<0))
+/** Receive TimeOut */
+#define SSP_MIS_RT ((uint32_t)(1<<1))
+/** Rx FIFO is at least half full */
+#define SSP_MIS_RX ((uint32_t)(1<<2))
+/** Tx FIFO is at least half empty */
+#define SSP_MIS_TX ((uint32_t)(1<<3))
+/** MIS bit mask */
+#define SSP_MIS_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro define for (ICR) Interrupt Clear registers
+ **********************************************************************/
+/** Writing a 1 to this bit clears the "frame was received when
+ * RxFIFO was full" interrupt */
+#define SSP_ICR_ROR ((uint32_t)(1<<0))
+/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
+ * has not been read for a timeout period" interrupt */
+#define SSP_ICR_RT ((uint32_t)(1<<1))
+/** ICR bit mask */
+#define SSP_ICR_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for DMACR register
+ **********************************************************************/
+/** SSP bit for enabling RX DMA */
+#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
+/** SSP bit for enabling TX DMA */
+#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
+/** DMACR bit mask */
+#define SSP_DMA_BITMASK ((uint32_t)(0x03))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid SSP port number */
+#define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
+
+/** Macro check clock phase control mode */
+#define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
+
+/** Macro check clock polarity mode */
+#define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
+
+/* Macro check master/slave mode */
+#define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
+
+/* Macro check databit value */
+#define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
+|| (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
+|| (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
+|| (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
+|| (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
+|| (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
+|| (n==SSP_DATABIT_15))
+
+/* Macro check frame type */
+#define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
+|| (n==SSP_FRAME_MICROWIRE))
+
+/* Macro check SSP status */
+#define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
+|| (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
+|| (n==SSP_STAT_BUSY))
+
+/* Macro check interrupt configuration */
+#define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
+|| (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
+
+/* Macro check interrupt status value */
+#define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
+|| (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
+
+/* Macro check interrupt status raw value */
+#define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
+|| (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
+
+/* Macro check interrupt clear mode */
+#define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
+
+/* Macro check DMA mode */
+#define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup SSP_Public_Types SSP Public Types
+ * @{
+ */
+
+/** @brief SSP configuration structure */
+typedef struct {
+ uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
+ where x is in range from 4 - 16 */
+ uint32_t CPHA; /** Clock phase, should be:
+ - SSP_CPHA_FIRST: first clock edge
+ - SSP_CPHA_SECOND: second clock edge */
+ uint32_t CPOL; /** Clock polarity, should be:
+ - SSP_CPOL_HI: high level
+ - SSP_CPOL_LO: low level */
+ uint32_t Mode; /** SSP mode, should be:
+ - SSP_MASTER_MODE: Master mode
+ - SSP_SLAVE_MODE: Slave mode */
+ uint32_t FrameFormat; /** Frame Format:
+ - SSP_FRAME_SPI: Motorola SPI frame format
+ - SSP_FRAME_TI: TI frame format
+ - SSP_FRAME_MICROWIRE: National Microwire frame format */
+ uint32_t ClockRate; /** Clock rate,in Hz */
+} SSP_CFG_Type;
+
+/**
+ * @brief SSP Transfer Type definitions
+ */
+typedef enum {
+ SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
+ SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
+} SSP_TRANSFER_Type;
+
+/**
+ * @brief SPI Data configuration structure definitions
+ */
+typedef struct {
+ void *tx_data; /**< Pointer to transmit data */
+ uint32_t tx_cnt; /**< Transmit counter */
+ void *rx_data; /**< Pointer to transmit data */
+ uint32_t rx_cnt; /**< Receive counter */
+ uint32_t length; /**< Length of transfer data */
+ uint32_t status; /**< Current status of SSP activity */
+} SSP_DATA_SETUP_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SSP_Public_Functions SSP Public Functions
+ * @{
+ */
+
+/* SSP Init/DeInit functions --------------------------------------------------*/
+void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
+void SSP_DeInit(LPC_SSP_TypeDef* SSPx);
+
+/* SSP configure functions ----------------------------------------------------*/
+void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
+
+/* SSP enable/disable functions -----------------------------------------------*/
+void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
+void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
+void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
+void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState);
+
+/* SSP get information functions ----------------------------------------------*/
+FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType);
+uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx);
+IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType);
+uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx);
+IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType);
+
+/* SSP transfer data functions ------------------------------------------------*/
+void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data);
+uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx);
+int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
+ SSP_TRANSFER_Type xfType);
+
+/* SSP IRQ function ------------------------------------------------------------*/
+void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState);
+void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType);
+
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_SSP_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_systick.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_systick.h new file mode 100644 index 0000000..6a243c2 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_systick.h @@ -0,0 +1,107 @@ +/***********************************************************************//**
+ * @file lpc17xx_systick.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for SYSTICK firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SYSTICK SYSTICK
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_SYSTICK_H_
+#define LPC17XX_SYSTICK_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup SYSTICK_Private_Macros SYSTICK Private Macros
+ * @{
+ */
+/*********************************************************************//**
+ * Macro defines for System Timer Control and status (STCTRL) register
+ **********************************************************************/
+#define ST_CTRL_ENABLE ((uint32_t)(1<<0))
+#define ST_CTRL_TICKINT ((uint32_t)(1<<1))
+#define ST_CTRL_CLKSOURCE ((uint32_t)(1<<2))
+#define ST_CTRL_COUNTFLAG ((uint32_t)(1<<16))
+
+/*********************************************************************//**
+ * Macro defines for System Timer Reload value (STRELOAD) register
+ **********************************************************************/
+#define ST_RELOAD_RELOAD(n) ((uint32_t)(n & 0x00FFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for System Timer Current value (STCURRENT) register
+ **********************************************************************/
+#define ST_RELOAD_CURRENT(n) ((uint32_t)(n & 0x00FFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for System Timer Calibration value (STCALIB) register
+ **********************************************************************/
+#define ST_CALIB_TENMS(n) ((uint32_t)(n & 0x00FFFFFF))
+#define ST_CALIB_SKEW ((uint32_t)(1<<30))
+#define ST_CALIB_NOREF ((uint32_t)(1<<31))
+
+#define CLKSOURCE_EXT ((uint32_t)(0))
+#define CLKSOURCE_CPU ((uint32_t)(1))
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SYSTICK_Public_Functions SYSTICK Public Functions
+ * @{
+ */
+
+void SYSTICK_InternalInit(uint32_t time);
+void SYSTICK_ExternalInit(uint32_t freq, uint32_t time);
+
+void SYSTICK_Cmd(FunctionalState NewState);
+void SYSTICK_IntCmd(FunctionalState NewState);
+uint32_t SYSTICK_GetCurrentValue(void);
+void SYSTICK_ClearCounterFlag(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_SYSTICK_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_timer.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_timer.h new file mode 100644 index 0000000..3b9d99d --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_timer.h @@ -0,0 +1,335 @@ +/***********************************************************************//**
+ * @file lpc17xx_timer.h
+ * @brief Contains all functions support for Timer firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup TIM TIM
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC17XX_TIMER_H_
+#define __LPC17XX_TIMER_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/**********************************************************************
+** Interrupt information
+**********************************************************************/
+/** Macro to clean interrupt pending */
+#define TIM_IR_CLR(n) _BIT(n)
+
+/**********************************************************************
+** Timer interrupt register definitions
+**********************************************************************/
+/** Macro for getting a timer match interrupt bit */
+#define TIM_MATCH_INT(n) (_BIT(n & 0x0F))
+/** Macro for getting a capture event interrupt bit */
+#define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4)))
+
+/**********************************************************************
+* Timer control register definitions
+**********************************************************************/
+/** Timer/counter enable bit */
+#define TIM_ENABLE ((uint32_t)(1<<0))
+/** Timer/counter reset bit */
+#define TIM_RESET ((uint32_t)(1<<1))
+/** Timer control bit mask */
+#define TIM_TCR_MASKBIT ((uint32_t)(3))
+
+/**********************************************************************
+* Timer match control register definitions
+**********************************************************************/
+/** Bit location for interrupt on MRx match, n = 0 to 3 */
+#define TIM_INT_ON_MATCH(n) (_BIT((n * 3)))
+/** Bit location for reset on MRx match, n = 0 to 3 */
+#define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1)))
+/** Bit location for stop on MRx match, n = 0 to 3 */
+#define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2)))
+/** Timer Match control bit mask */
+#define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF))
+/** Timer Match control bit mask for specific channel*/
+#define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
+
+/**********************************************************************
+* Timer capture control register definitions
+**********************************************************************/
+/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
+#define TIM_CAP_RISING(n) (_BIT((n * 3)))
+/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
+#define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1)))
+/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
+#define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2)))
+/** Mask bit for rising and falling edge bit */
+#define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03))
+/** Timer capture control bit mask */
+#define TIM_CCR_MASKBIT ((uint32_t)(0x3F))
+/** Timer Capture control bit mask for specific channel*/
+#define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
+
+/**********************************************************************
+* Timer external match register definitions
+**********************************************************************/
+/** Bit location for output state change of MAT.n when external match
+ happens, n = 0 to 3 */
+#define TIM_EM(n) _BIT(n)
+/** Output state change of MAT.n when external match happens: no change */
+#define TIM_EM_NOTHING ((uint8_t)(0x0))
+/** Output state change of MAT.n when external match happens: low */
+#define TIM_EM_LOW ((uint8_t)(0x1))
+/** Output state change of MAT.n when external match happens: high */
+#define TIM_EM_HIGH ((uint8_t)(0x2))
+/** Output state change of MAT.n when external match happens: toggle */
+#define TIM_EM_TOGGLE ((uint8_t)(0x3))
+/** Macro for setting for the MAT.n change state bits */
+#define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03)))
+/** Mask for the MAT.n change state bits */
+#define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03))
+/** Timer external match bit mask */
+#define TIM_EMR_MASKBIT 0x0FFF
+
+/**********************************************************************
+* Timer Count Control Register definitions
+**********************************************************************/
+/** Mask to get the Counter/timer mode bits */
+#define TIM_CTCR_MODE_MASK 0x3
+/** Mask to get the count input select bits */
+#define TIM_CTCR_INPUT_MASK 0xC
+/** Timer Count control bit mask */
+#define TIM_CTCR_MASKBIT 0xF
+#define TIM_COUNTER_MODE ((uint8_t)(1))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid TIMER peripheral */
+#define PARAM_TIMx(n) ((((uint32_t *)n)==((uint32_t *)LPC_TIM0)) || (((uint32_t *)n)==((uint32_t *)LPC_TIM1)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_TIM2)) || (((uint32_t *)n)==((uint32_t *)LPC_TIM3)))
+
+/* Macro check interrupt type */
+#define PARAM_TIM_INT_TYPE(TYPE) ((TYPE ==TIM_MR0_INT)||(TYPE ==TIM_MR1_INT)\
+||(TYPE ==TIM_MR2_INT)||(TYPE ==TIM_MR3_INT)\
+||(TYPE ==TIM_CR0_INT)||(TYPE ==TIM_CR1_INT))
+
+/* Macro check TIMER mode */
+#define PARAM_TIM_MODE_OPT(MODE) ((MODE == TIM_TIMER_MODE)||(MODE == TIM_COUNTER_RISING_MODE)\
+|| (MODE == TIM_COUNTER_RISING_MODE)||(MODE == TIM_COUNTER_RISING_MODE))
+
+/* Macro check TIMER prescale value */
+#define PARAM_TIM_PRESCALE_OPT(OPT) ((OPT == TIM_PRESCALE_TICKVAL)||(OPT == TIM_PRESCALE_USVAL))
+
+/* Macro check TIMER counter intput mode */
+#define PARAM_TIM_COUNTER_INPUT_OPT(OPT) ((OPT == TIM_COUNTER_INCAP0)||(OPT == TIM_COUNTER_INCAP1))
+
+/* Macro check TIMER external match mode */
+#define PARAM_TIM_EXTMATCH_OPT(OPT) ((OPT == TIM_EXTMATCH_NOTHING)||(OPT == TIM_EXTMATCH_LOW)\
+||(OPT == TIM_EXTMATCH_HIGH)||(OPT == TIM_EXTMATCH_TOGGLE))
+
+/* Macro check TIMER external match mode */
+#define PARAM_TIM_CAP_MODE_OPT(OPT) ((OPT == TIM_CAPTURE_NONE)||(OPT == TIM_CAPTURE_RISING) \
+||(OPT == TIM_CAPTURE_FALLING)||(OPT == TIM_CAPTURE_ANY))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup TIM_Public_Types TIM Public Types
+ * @{
+ */
+
+/***********************************************************************
+ * Timer device enumeration
+**********************************************************************/
+/** @brief interrupt type */
+typedef enum
+{
+ TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/
+ TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/
+ TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/
+ TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/
+ TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/
+ TIM_CR1_INT =5, /*!< interrupt for Capture channel 1*/
+}TIM_INT_TYPE;
+
+/** @brief Timer/counter operating mode */
+typedef enum
+{
+ TIM_TIMER_MODE = 0, /*!< Timer mode */
+ TIM_COUNTER_RISING_MODE, /*!< Counter rising mode */
+ TIM_COUNTER_FALLING_MODE, /*!< Counter falling mode */
+ TIM_COUNTER_ANY_MODE /*!< Counter on both edges */
+} TIM_MODE_OPT;
+
+/** @brief Timer/Counter prescale option */
+typedef enum
+{
+ TIM_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */
+ TIM_PRESCALE_USVAL /*!< Prescale in microsecond value */
+} TIM_PRESCALE_OPT;
+
+/** @brief Counter input option */
+typedef enum
+{
+ TIM_COUNTER_INCAP0 = 0, /*!< CAPn.0 input pin for TIMERn */
+ TIM_COUNTER_INCAP1, /*!< CAPn.1 input pin for TIMERn */
+} TIM_COUNTER_INPUT_OPT;
+
+/** @brief Timer/Counter external match option */
+typedef enum
+{
+ TIM_EXTMATCH_NOTHING = 0, /*!< Do nothing for external output pin if match */
+ TIM_EXTMATCH_LOW, /*!< Force external output pin to low if match */
+ TIM_EXTMATCH_HIGH, /*!< Force external output pin to high if match */
+ TIM_EXTMATCH_TOGGLE /*!< Toggle external output pin if match */
+}TIM_EXTMATCH_OPT;
+
+/** @brief Timer/counter capture mode options */
+typedef enum {
+ TIM_CAPTURE_NONE = 0, /*!< No Capture */
+ TIM_CAPTURE_RISING, /*!< Rising capture mode */
+ TIM_CAPTURE_FALLING, /*!< Falling capture mode */
+ TIM_CAPTURE_ANY /*!< On both edges */
+} TIM_CAP_MODE_OPT;
+
+/** @brief Configuration structure in TIMER mode */
+typedef struct
+{
+
+ uint8_t PrescaleOption; /**< Timer Prescale option, should be:
+ - TIM_PRESCALE_TICKVAL: Prescale in absolute value
+ - TIM_PRESCALE_USVAL: Prescale in microsecond value
+ */
+ uint8_t Reserved[3]; /**< Reserved */
+ uint32_t PrescaleValue; /**< Prescale value */
+} TIM_TIMERCFG_Type;
+
+/** @brief Configuration structure in COUNTER mode */
+typedef struct {
+
+ uint8_t CounterOption; /**< Counter Option, should be:
+ - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
+ - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
+ */
+ uint8_t CountInputSelect;
+ uint8_t Reserved[2];
+} TIM_COUNTERCFG_Type;
+
+/** @brief Match channel configuration structure */
+typedef struct {
+ uint8_t MatchChannel; /**< Match channel, should be in range
+ from 0..3 */
+ uint8_t IntOnMatch; /**< Interrupt On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+ uint8_t StopOnMatch; /**< Stop On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+ uint8_t ResetOnMatch; /**< Reset On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+
+ uint8_t ExtMatchOutputType; /**< External Match Output type, should be:
+ - TIM_EXTMATCH_NOTHING: Do nothing for external output pin if match
+ - TIM_EXTMATCH_LOW: Force external output pin to low if match
+ - TIM_EXTMATCH_HIGH: Force external output pin to high if match
+ - TIM_EXTMATCH_TOGGLE: Toggle external output pin if match.
+ */
+ uint8_t Reserved[3]; /** Reserved */
+ uint32_t MatchValue; /** Match value */
+} TIM_MATCHCFG_Type;
+
+/** @brief Capture Input configuration structure */
+typedef struct {
+ uint8_t CaptureChannel; /**< Capture channel, should be in range
+ from 0..1 */
+ uint8_t RisingEdge; /**< caption rising edge, should be:
+ - ENABLE: Enable rising edge.
+ - DISABLE: Disable this function.
+ */
+ uint8_t FallingEdge; /**< caption falling edge, should be:
+ - ENABLE: Enable falling edge.
+ - DISABLE: Disable this function.
+ */
+ uint8_t IntOnCaption; /**< Interrupt On caption, should be:
+ - ENABLE: Enable interrupt function.
+ - DISABLE: Disable this function.
+ */
+
+} TIM_CAPTURECFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup TIM_Public_Functions TIM Public Functions
+ * @{
+ */
+/* Init/DeInit TIM functions -----------*/
+void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
+void TIM_DeInit(LPC_TIM_TypeDef *TIMx);
+
+/* TIM interrupt functions -------------*/
+void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
+void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
+FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
+FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
+
+/* TIM configuration functions --------*/
+void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
+void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct);
+void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue);
+void TIM_SetMatchExt(LPC_TIM_TypeDef *TIMx,TIM_EXTMATCH_OPT ext_match );
+void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct);
+void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState);
+
+uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel);
+void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx);
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC17XX_TIMER_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_uart.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_uart.h new file mode 100644 index 0000000..3156b10 --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_uart.h @@ -0,0 +1,644 @@ +/***********************************************************************//**
+ * @file lpc17xx_uart.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for UART firmware library on LPC17xx
+ * @version 3.0
+ * @date 18. June. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup UART UART
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC17XX_UART_H
+#define __LPC17XX_UART_H
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup UART_Public_Macros UART Public Macros
+ * @{
+ */
+
+/** UART time-out definitions in case of using Read() and Write function
+ * with Blocking Flag mode
+ */
+#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+
+/* Accepted Error baud rate value (in percent unit) */
+#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Receiver Buffer Register
+ **********************************************************************/
+#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Transmit Holding Register
+ **********************************************************************/
+#define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch LSB register
+ **********************************************************************/
+#define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */
+#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch MSB register
+ **********************************************************************/
+#define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */
+#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt enable register
+ **********************************************************************/
+#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/
+#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/
+#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/
+#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */
+#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */
+#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */
+#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */
+#define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
+#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt identification register
+ **********************************************************************/
+#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */
+#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/
+#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/
+#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/
+#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/
+#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/
+#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */
+#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */
+#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */
+#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */
+#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO control register
+ **********************************************************************/
+#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */
+#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */
+#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */
+#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */
+#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */
+#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */
+#define UART_TX_FIFO_SIZE (16)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line control register
+ **********************************************************************/
+#define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */
+#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */
+#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */
+#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */
+#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */
+#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */
+#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */
+#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */
+#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */
+#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */
+#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */
+#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */
+#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 Modem Control Register
+ **********************************************************************/
+#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */
+#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */
+#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */
+#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */
+#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */
+#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line status register
+ **********************************************************************/
+#define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/
+#define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/
+#define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/
+#define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/
+#define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/
+#define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/
+#define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/
+#define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/
+#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Modem (UART1 only) status register
+ **********************************************************************/
+#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */
+#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */
+#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */
+#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */
+#define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */
+#define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */
+#define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */
+#define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */
+#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Scratch Pad Register
+ **********************************************************************/
+#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Auto baudrate control register
+ **********************************************************************/
+#define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */
+#define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */
+#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */
+#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */
+#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */
+#define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART IrDA control register
+ **********************************************************************/
+#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */
+#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */
+#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */
+#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Fractional divider register
+ **********************************************************************/
+#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */
+#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */
+#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Tx Enable register
+ **********************************************************************/
+#define UART_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */
+#define UART_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS485 Control register
+ **********************************************************************/
+#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
+ is disabled */
+#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */
+#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */
+#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled
+ (bit DCTRL = 1), pin DTR is used for direction control */
+#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */
+#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction
+ control signal on the RTS (or DTR) pin. The direction control pin
+ will be driven to logic "1" when the transmitter has data to be sent */
+#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Address Match register
+ **********************************************************************/
+#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Delay value register
+ **********************************************************************/
+/* Macro defines for UART1 RS-485 Delay value register */
+#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO Level register
+ **********************************************************************/
+#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */
+#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */
+#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+
+/** Macro to check the input UART_DATABIT parameters */
+#define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\
+|| (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))
+
+/** Macro to check the input UART_STOPBIT parameters */
+#define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))
+
+/** Macro to check the input UART_PARITY parameters */
+#define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \
+|| (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \
+|| (parity==UART_PARITY_SP_0))
+
+/** Macro to check the input UART_FIFO parameters */
+#define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \
+|| (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \
+|| (fifo==UART_FIFO_TRGLEV3))
+
+/** Macro to check the input UART_INTCFG parameters */
+#define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \
+|| (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \
+|| (IntCfg==UART_INTCFG_ABTO))
+
+/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
+#define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))
+
+/** Macro to check the input UART_AUTOBAUD_MODE parameters */
+#define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))
+
+/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
+#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \
+ (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
+
+/** Macro to check the input UART_IrDA_PULSEDIV parameters */
+#define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \
+|| (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \
+|| (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \
+|| (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))
+
+/* Macro to check the input UART1_SignalState parameters */
+#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))
+
+/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
+#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))
+
+/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
+#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \
+|| (x==UART1_MODEM_MODE_AUTO_CTS))
+
+/** Macro to check the direction control pin type */
+#define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR))
+
+/* Macro to determine if it is valid UART port number */
+#define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART3)))
+#define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3))
+#define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))
+
+/** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */
+#define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
+
+/** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */
+#define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup UART_Public_Types UART Public Types
+ * @{
+ */
+
+/**
+ * @brief UART Databit type definitions
+ */
+typedef enum {
+ UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
+ UART_DATABIT_6, /*!< UART 6 bit data mode */
+ UART_DATABIT_7, /*!< UART 7 bit data mode */
+ UART_DATABIT_8 /*!< UART 8 bit data mode */
+} UART_DATABIT_Type;
+
+/**
+ * @brief UART Stop bit type definitions
+ */
+typedef enum {
+ UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
+ UART_STOPBIT_2, /*!< UART Two Stop Bits Select */
+} UART_STOPBIT_Type;
+
+/**
+ * @brief UART Parity type definitions
+ */
+typedef enum {
+ UART_PARITY_NONE = 0, /*!< No parity */
+ UART_PARITY_ODD, /*!< Odd parity */
+ UART_PARITY_EVEN, /*!< Even parity */
+ UART_PARITY_SP_1, /*!< Forced "1" stick parity */
+ UART_PARITY_SP_0 /*!< Forced "0" stick parity */
+} UART_PARITY_Type;
+
+/**
+ * @brief FIFO Level type definitions
+ */
+typedef enum {
+ UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
+ UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
+ UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
+ UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
+} UART_FITO_LEVEL_Type;
+
+/********************************************************************//**
+* @brief UART Interrupt Type definitions
+**********************************************************************/
+typedef enum {
+ UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
+ UART_INTCFG_THRE, /*!< THR Interrupt enable*/
+ UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
+ UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
+ UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
+ UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
+ UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
+} UART_INT_Type;
+
+/**
+ * @brief UART Line Status Type definition
+ */
+typedef enum {
+ UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
+ UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
+ UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
+ UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
+ UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
+ UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
+ UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
+ UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
+} UART_LS_Type;
+
+/**
+ * @brief UART Auto-baudrate mode type definition
+ */
+typedef enum {
+ UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
+ UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */
+} UART_AB_MODE_Type;
+
+/**
+ * @brief Auto Baudrate mode configuration type definition
+ */
+typedef struct {
+ UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
+ FunctionalState AutoRestart; /**< Auto Restart state */
+} UART_AB_CFG_Type;
+
+/**
+ * @brief UART End of Auto-baudrate type definition
+ */
+typedef enum {
+ UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
+ UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
+}UART_ABEO_Type;
+
+/**
+ * UART IrDA Control type Definition
+ */
+typedef enum {
+ UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+} UART_IrDA_PULSE_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem - Signal states definition
+**********************************************************************/
+typedef enum {
+ INACTIVE = 0, /* In-active state */
+ ACTIVE = !INACTIVE /* Active state */
+}UART1_SignalState;
+
+/**
+ * @brief UART modem status type definition
+ */
+typedef enum {
+ UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
+ UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
+ UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
+ UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
+ UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
+ UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
+ UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
+ UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
+} UART_MODEM_STAT_type;
+
+/**
+ * @brief Modem output pin type definition
+ */
+typedef enum {
+ UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
+ UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
+} UART_MODEM_PIN_Type;
+
+/**
+ * @brief UART Modem mode type definition
+ */
+typedef enum {
+ UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
+ UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
+ UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
+} UART_MODEM_MODE_Type;
+
+/**
+ * @brief UART Direction Control Pin type definition
+ */
+typedef enum {
+ UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
+ UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */
+} UART_RS485_DIRCTRL_PIN_Type;
+
+/********************************************************************//**
+* @brief UART Configuration Structure definition
+**********************************************************************/
+typedef struct {
+ uint32_t Baud_rate; /**< UART baud rate */
+ UART_PARITY_Type Parity; /**< Parity selection, should be:
+ - UART_PARITY_NONE: No parity
+ - UART_PARITY_ODD: Odd parity
+ - UART_PARITY_EVEN: Even parity
+ - UART_PARITY_SP_1: Forced "1" stick parity
+ - UART_PARITY_SP_0: Forced "0" stick parity
+ */
+ UART_DATABIT_Type Databits; /**< Number of data bits, should be:
+ - UART_DATABIT_5: UART 5 bit data mode
+ - UART_DATABIT_6: UART 6 bit data mode
+ - UART_DATABIT_7: UART 7 bit data mode
+ - UART_DATABIT_8: UART 8 bit data mode
+ */
+ UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
+ - UART_STOPBIT_1: UART 1 Stop Bits Select
+ - UART_STOPBIT_2: UART 2 Stop Bits Select
+ */
+} UART_CFG_Type;
+
+/********************************************************************//**
+* @brief UART FIFO Configuration Structure definition
+**********************************************************************/
+
+typedef struct {
+ FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
+ - ENABLE: Reset Rx FIFO in UART
+ - DISABLE: Do not reset Rx FIFO in UART
+ */
+ FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
+ - ENABLE: Reset Tx FIFO in UART
+ - DISABLE: Do not reset Tx FIFO in UART
+ */
+ FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
+ - ENABLE: Enable DMA mode in UART
+ - DISABLE: Disable DMA mode in UART
+ */
+ UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
+ - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
+ - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
+ - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
+ - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
+ */
+} UART_FIFO_CFG_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem - RS485 Control configuration type
+**********************************************************************/
+typedef struct {
+ FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function. */
+ FunctionalState Rx_State; /*!< Receiver State:
+ - ENABLE: Enable Receiver.
+ - DISABLE: Disable Receiver. */
+ FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
+ - ENABLE: ENABLE this function.
+ - DISABLE: Disable this function. */
+ FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function. */
+ UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
+ - UART1_RS485_DIRCTRL_RTS:
+ pin RTS is used for direction control.
+ - UART1_RS485_DIRCTRL_DTR:
+ pin DTR is used for direction control. */
+ SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
+ the RTS (or DTR) pin:
+ - RESET: The direction control pin will be driven
+ to logic "0" when the transmitter has data to be sent.
+ - SET: The direction control pin will be driven
+ to logic "1" when the transmitter has data to be sent. */
+ uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
+ uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
+} UART1_RS485_CTRLCFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup UART_Public_Functions UART Public Functions
+ * @{
+ */
+/* UART Init/DeInit functions --------------------------------------------------*/
+void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct);
+void UART_DeInit(LPC_UART_TypeDef* UARTx);
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
+
+/* UART Send/Receive functions -------------------------------------------------*/
+void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data);
+uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx);
+uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
+ uint32_t buflen, TRANSFER_BLOCK_Type flag);
+uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
+ uint32_t buflen, TRANSFER_BLOCK_Type flag);
+
+/* UART FIFO functions ----------------------------------------------------------*/
+void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
+
+/* UART get information functions -----------------------------------------------*/
+uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx);
+uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
+
+/* UART operate functions -------------------------------------------------------*/
+void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
+ FunctionalState NewState);
+void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
+FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
+void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
+
+/* UART Auto-baud functions -----------------------------------------------------*/
+void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType);
+void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
+ FunctionalState NewState);
+
+/* UART1 FullModem functions ----------------------------------------------------*/
+void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
+ UART1_SignalState NewState);
+void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
+ FunctionalState NewState);
+uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
+
+/* UART RS485 functions ----------------------------------------------------------*/
+void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \
+ UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
+void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState);
+void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr);
+uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size);
+
+/* UART IrDA functions-------------------------------------------------------------*/
+void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv);
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __LPC17XX_UART_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc17xx_wdt.h b/arch/arm/lpc17xx/Drivers/include/lpc17xx_wdt.h new file mode 100644 index 0000000..651188f --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc17xx_wdt.h @@ -0,0 +1,142 @@ +/***********************************************************************//**
+ * @file lpc17xx_wdt.h
+ * @brief Contains all macro definitions and function prototypes
+ * support for WDT firmware library on LPC17xx
+ * @version 2.0
+ * @date 21. May. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup WDT WDT
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_WDT_H_
+#define LPC17XX_WDT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup WDT_Private_Macros WDT Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/** WDT interrupt enable bit */
+#define WDT_WDMOD_WDEN ((uint32_t)(1<<0))
+/** WDT interrupt enable bit */
+#define WDT_WDMOD_WDRESET ((uint32_t)(1<<1))
+/** WDT time out flag bit */
+#define WDT_WDMOD_WDTOF ((uint32_t)(1<<2))
+/** WDT Time Out flag bit */
+#define WDT_WDMOD_WDINT ((uint32_t)(1<<3))
+/** WDT Mode */
+#define WDT_WDMOD(n) ((uint32_t)(1<<1))
+
+/** Define divider index for microsecond ( us ) */
+#define WDT_US_INDEX ((uint32_t)(1000000))
+/** WDT Time out minimum value */
+#define WDT_TIMEOUT_MIN ((uint32_t)(0xFF))
+/** WDT Time out maximum value */
+#define WDT_TIMEOUT_MAX ((uint32_t)(0xFFFFFFFF))
+
+/** Watchdog mode register mask */
+#define WDT_WDMOD_MASK (uint8_t)(0x02)
+/** Watchdog timer constant register mask */
+#define WDT_WDTC_MASK (uint8_t)(0xFFFFFFFF)
+/** Watchdog feed sequence register mask */
+#define WDT_WDFEED_MASK (uint8_t)(0x000000FF)
+/** Watchdog timer value register mask */
+#define WDT_WDCLKSEL_MASK (uint8_t)(0x03)
+/** Clock selected from internal RC */
+#define WDT_WDCLKSEL_RC (uint8_t)(0x00)
+/** Clock selected from PCLK */
+#define WDT_WDCLKSEL_PCLK (uint8_t)(0x01)
+/** Clock selected from external RTC */
+#define WDT_WDCLKSEL_RTC (uint8_t)(0x02)
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macro check clock source selection */
+#define PARAM_WDT_CLK_OPT(OPTION) ((OPTION ==WDT_CLKSRC_IRC)||(OPTION ==WDT_CLKSRC_IRC)\
+||(OPTION ==WDT_CLKSRC_IRC))
+
+/* Macro check WDT mode */
+#define PARAM_WDT_MODE_OPT(OPTION) ((OPTION ==WDT_MODE_INT_ONLY)||(OPTION ==WDT_MODE_RESET))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup WDT_Public_Types WDT Public Types
+ * @{
+ */
+
+/** @brief Clock source option for WDT */
+typedef enum {
+ WDT_CLKSRC_IRC = 0, /*!< Clock source from Internal RC oscillator */
+ WDT_CLKSRC_PCLK = 1, /*!< Selects the APB peripheral clock (PCLK) */
+ WDT_CLKSRC_RTC = 2 /*!< Selects the RTC oscillator */
+} WDT_CLK_OPT;
+
+/** @brief WDT operation mode */
+typedef enum {
+ WDT_MODE_INT_ONLY = 0, /*!< Use WDT to generate interrupt only */
+ WDT_MODE_RESET = 1 /*!< Use WDT to generate interrupt and reset MCU */
+} WDT_MODE_OPT;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup WDT_Public_Functions WDT Public Functions
+ * @{
+ */
+
+void WDT_Init (WDT_CLK_OPT ClkSrc, WDT_MODE_OPT WDTMode);
+void WDT_Start(uint32_t TimeOut);
+void WDT_Feed (void);
+void WDT_UpdateTimeOut ( uint32_t TimeOut);
+FlagStatus WDT_ReadTimeOutFlag (void);
+void WDT_ClrTimeOutFlag (void);
+uint32_t WDT_GetCurrentCount(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_WDT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/arch/arm/lpc17xx/Drivers/include/lpc_types.h b/arch/arm/lpc17xx/Drivers/include/lpc_types.h new file mode 100644 index 0000000..9cfb3be --- /dev/null +++ b/arch/arm/lpc17xx/Drivers/include/lpc_types.h @@ -0,0 +1,196 @@ +/***********************************************************************//**
+ * @file lpc_types.h
+ * @brief Contains the NXP ABL typedefs for C standard types.
+ * It is intended to be used in ISO C conforming development
+ * environments and checks for this insofar as it is possible
+ * to do so.
+ * @version 1.0
+ * @date 27 Jul. 2008
+ * @author wellsk
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Type group ----------------------------------------------------------- */
+/** @defgroup LPC_Types LPC_Types
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC_TYPES_H
+#define LPC_TYPES_H
+
+/* Includes ------------------------------------------------------------------- */
+#include <stdint.h>
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum
+{
+ NONE_BLOCKING = 0, /**< None Blocking type */
+ BLOCKING, /**< Blocking type */
+} TRANSFER_BLOCK_Type;
+
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t(*PFI)();
+
+/**
+ * @}
+ */
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
+ * @{
+ */
+
+/* _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/* Set bit macro */
+#define _BIT(n) (1<<n)
+
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f,v) (v<<f)
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off. When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+/**
+ * @}
+ */
+
+
+/* Old Type Definition compatibility ------------------------------------------ */
+/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/** SMA type for character type */
+typedef char CHAR;
+
+/** SMA type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** SMA type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** SMA type for 16 bit unsigned value */
+typedef uint16_t UNS_16;
+
+/** SMA type for 16 bit signed value */
+typedef int16_t INT_16;
+
+/** SMA type for 32 bit unsigned value */
+typedef uint32_t UNS_32;
+
+/** SMA type for 32 bit signed value */
+typedef int32_t INT_32;
+
+/** SMA type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** SMA type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+/** 32 bit boolean type */
+typedef Bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef Bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef Bool BOOL_8;
+
+/**
+ * @}
+ */
+
+
+#endif /* LPC_TYPES_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
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